HOW TO PERMANENTLY PROGAM NEXY4 DDR

[fLx]

Good day, please i tried to compile my project and followed the digilent guide on how to program the flash memory of digilent board from xilinx sdk, but to my surprise is that it only program the bit configuration of my project and i'l have to press run on sdk before the system starts working......please i want it to commense the system operation without having to run it any longer from the sdk....please any help on this????????????????????/

[fLx]

@jpeyron , i used 50MHz for the ext_spi_clk on the spi flash ip core.....attached is my block design and messages from each step

[jpeyron]

Hi @fLx,

I do not believe that using an evaluation copy would limit this usage. You can contact xilinx to get a definitive answer. You could also use the vivado 2017.3 webpack edition which is free as well. Did you load  one of the projects i made and just launched it from sdk? Once the sdk is open you program the fpga and then the flash memory first the elf and then the download bit. Make sue the mode jumper is set to qspi while you are doing this.  Did you make sure to change the elf/mem file to initialize in block ram in the program fpga step?

thank you,

Jon

[fLx]

On 23/02/2018 at 2:13 AM, jpeyron said:

Hi @flexible111,

I had a hard time getting your project to load correctly on my PC. I made two different projects in Vivado 2017.3 one with a non-compressed bitstream and one with a compressed bitstream and verbose is commented out in the srec bootloader so the project loads super fast. You will need to install the board files following the Vivado Version 2015.1 and Later Board File Installation tutorial. When you open either project first go into the project setting and set the IP repo to your vivado library path. Then you can open the block design and see what the block design looks like. You do not need to generate the bitsream again you can just launch SDK using the existing bitstream. Once SDK opens you will program the fpga and then load the .elf  file with the offset as 0x003D0900 for either project and download.bit file (0x0) with the mode jumper on qspi. Then you should only need to turn off the Nexys 4 DDR and turn it back on. I used the same Pmod port JC as was in your project. Here is the non-compressed project and here is the compressed project. The compressed project will not send information out through the uart since I commented out verbose in the bootloader.c in the srec application.

thank you,

Jon

Good day @jpeyron, could an evaluation copy of xilinx vivado and sdk cause the board not to load sdk program when powered ON.......because i'v tried all procedure carefully .. but still having the problem unsolved.

[fLx]

Good day @jpeyron, could an evaluation copy of xilinx vivado and sdk cause the board not to load sdk program when powered ON.......because i'v tried procedure carefully .. but still having the problem unsolved. ...tired of it

[jpeyron]

Hi @flexible111,

I had a hard time getting your project to load correctly on my PC. I made two different projects in Vivado 2017.3 one with a non-compressed bitstream and one with a compressed bitstream and verbose is commented out in the srec bootloader so the project loads super fast. You will need to install the board files following the Vivado Version 2015.1 and Later Board File Installation tutorial. When you open either project first go into the project setting and set the IP repo to your vivado library path. Then you can open the block design and see what the block design looks like. You do not need to generate the bitsream again you can just launch SDK using the existing bitstream. Once SDK opens you will program the fpga and then load the .elf  file with the offset as 0x003D0900 for either project and download.bit file (0x0) with the mode jumper on qspi. Then you should only need to turn off the Nexys 4 DDR and turn it back on. I used the same Pmod port JC as was in your project. Here is the non-compressed project and here is the compressed project. The compressed project will not send information out through the uart since I commented out verbose in the bootloader.c in the srec application.

thank you,

Jon

[jpeyron]

Hi @flexible111,

I apologize, I was out of the office the last couple of days and did not have access to a Nexys 4DDR. I will get to this as soon as I can. I am sorry for the inconvenience. It may be a couple of days due to activity on the forums.

thank you,

Jon

[fLx]

On 16/02/2018 at 9:52 PM, jpeyron said:

Hi @flexible111,

Using the board file along with the JA, JB...  ports should not effect the use of the flash. Here is the Vivado Version 2015.1 and Later Board File Installation tutorial.

To clarify you have the mode jumper JP1 set to spi flash? I left the jumper set to spi flash to program the Nexys 4 DDR and left it set to spi flash when powering on the board.

Can you share your project so i can try get your working from the flash?

thak you,

Jon

@jpeyron,  Good day.........i'v not gotten any response since i attached d link to my project?????????

[fLx]

the project can be downloaded from here: https://drive.google.com/open?id=1uPGOjPMkFhQ_B7TPsddDo4oDx2lN1prz

i'm using Vivado 2017.3

[jpeyron]

Hi @flexible111,

Using the board file along with the JA, JB...  ports should not effect the use of the flash. Here is the Vivado Version 2015.1 and Later Board File Installation tutorial.

To clarify you have the mode jumper JP1 set to spi flash? I left the jumper set to spi flash to program the Nexys 4 DDR and left it set to spi flash when powering on the board.

Can you share your project so i can try get your working from the flash?

thank you,

Jon

[fLx]

@jpeyron , please can you attach a baord file which contain the JA,JB,JC,JD ports

[fLx]

Thank you very much @jpeyron,  Yes i'm using the download.bit............i'm not using pmod port JA,JB,JC or JD because i couldn't find them in my ip file so what i used to do is to set it as external and constrain the pins in the xdc.....could that be the caus of it, how will i get the pmod port to my ip file?..... and besides, it do work if i run it ...just that the parmanent programming aspect is giving me issue.

[jpeyron]

Hi @flexible111,

Are you using the download.bit when you are programming the hw_platform? I have attached my sdk log, screen shot of my block design, screen shot of the programming process as well as a youtube video of it loading from flash with tera term data(sorry the video is sideways). From your screen shot it looks like you are not using the pmod ports from the board file but rather constrained the pins in the xdc. In my block design and youtube video you can see I am using Pmod Port JB.

thank you,

Jon

 

 

Nexys_4_ddr_flash_sdk_text.txt

[jpeyron]

Hi @flexible111,

I am sorry to hear you are still having issues with storing your project in flash.  I was able to get our PmodOLEDrgb example to run from flash as described on my February 6th post. The project loads from flash and executes the c code from power on.  Can you attach your project and a screen shot of your block design? Are you using a 50 MHz clock from the clocking wizard to the ext_spi_clk on the quad spi flash ip core? 

thank you,

Jon

[fLx]

Good day,..Pls concerning the permanent programming of the standalone project , Still not getting the result as i expected it to ......

firstly, i'm expecting it to run the project by it self when powered on, but what the board does is programming the .bit file alone .

take for instanse, i want to display some string on the oledrgb without having to introduce a system to run the project from sdk.

Or is it that, the "HOW TO STORE PROJECTCT IN SPI FLASH REFERENCE" provided by Digilent is just for the board to be configured with .bit file alone.?

Or is there something that i'm not getting right?

i carefully followed the process and everything was successful......when i reset the board , it programs itself but every instruction from the c programing is not being programmed.

i'l have to press run from the sdk before it now start to execute the .c file on the board.........

because if it's going to be working that way, then i'v wasted all my efforts and investement on Digilent Board.....................pls what's the solution?

[jpeyron]

Hi @flexible111,

That is correct 0x003D0900 gives the offset of 4 MB.

cheers,

Jon

[fLx]

if i'm right 0x003D0900 will hold for a size range to 4Mb?

[jpeyron]

Hi @flexible111,

It depends on the size of the compressed bitstream. You will have to do some MB to hex conversion to get the best offset for the compressed bitstream. My understanding is that you can still use the 0x003D0900 as an offset if you are not able to to get a better offset.

cheers,

Jon

[fLx]

thank you very much @jpeyron.  i did not get any error while programming it...i got a message stating the process was successful .... what if i'm using compressed bitstream , how do i know the ofsset to be used for the FLASH _IMAGE_BASEADDR in the blconfig.h?...thank you.

[jpeyron]

HI @flexible111,

I was able to get the Pmod OLEDrgb IP core example to load into flash. Here is the completed project. I needed to use 0x003D0900 as the FLASH_IMAGE_BASEADDR in the blconfig.h as well as the offset for the elf file in step 4.1 of the How To Store Your SDK Project in SPI Flash tutorial. I have also updated the How To Store Your SDK Project in SPI Flash tutorial to reflect this for the Nexys 4 DDR in step 1.3. It will take a little bit of time to finish loading up the project from flash if you do not comment out verbose as discussed in the How To Store Your SDK Project in SPI Flash tutorial.

cheers,

Jon

[jpeyron]

Hi @flexible111,

Are there any errors/warning with you sdk code. Are you able to share you project? 

cheers,

Jon

[fLx]

good day,  here is my block design ,....i'l have to press run before getting an output on the OLEdrgb ......and i want it to run by itself immediately when powered ,....just as a microcontrollers does.

[jpeyron]

Hi @flexible111,

Are you using the How To Store Your SDK Project in SPI Flash tutorial? If so when you follow the tutorial and program the nexys 4 ddr from sdk do you have the mode jumper JP1 set to QSPI? After this you unplug the power and then re-plug in power leaving the JP1 jumper on QSPI and the project should launch from the flash. Please attach sdk log in a text file and a screen shoot of your block design if posible. Does you project have the QSPI IP core added to the block design? Did you attach a 50 MHz clock from the clocking wizard to the ext_spi_clk on the QSPI IP core?

thank you,

Jon

[xc6lx45]

Hi,

"DDR" is volatile RAM memory so there is no direct way to store its contents permanently.
What you probably need is a "boot loader", a small piece of self-contained code that shovels data from Flash to DRAM and then launches the main application.