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yassinema2018

Zybo placing error

Question

i'm trying to make a pwm module that i want to use later with the sdk 

the module has two 32 bit inputs, the first is pwm up time and the second is pwmperiod 

 

the simulation is good but when i tried to implement the design, i had an placing error ( number of unplaced terminals is greater ....)

as i understand vivado tries to give the two inputs a port with 64 bits

my purpose is to assign a value to them from the sdk 

i tried declaring them as wires, integers, reg     same error

module pwm(
    input clk,
    input enable,
    output pwm_out,
   input [31:0]  pwm_val,
    input [31:0] pwm_period
    );

the log file is attached , thank you 

 

 

implem_log.txt

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I think there is a confusion. I am not talking about IO buffer (i.e., "physical ports") here. A port list is a list of inputs and outputs of your module as you declared here:

1 hour ago, yassinema2018 said:

module pwm( input clk, input enable, output pwm_out, input [31:0] pwm_val, input [31:0] pwm_period );

Vivado needs a top module. The top module contains a port list that Vivado is going to wire to physical pins. Your top module is pwm that's why Vivado does what it did. Instead, use a top module that instantiates axi and pwm like so:

top_module (
    output pwm_out,
    inout DDR_...
    ...
    inout FIXED_IO...
    ... 
    
);

Vivado tries automatically to figure out which is your top module. If you have more than one hierarchie it picks whatever. In this case you can manually tell Vivado which your top module is.

 

To put it simple: remove all inputs and outputs in your top module that you don't want Vivado to wire at pins.

Edited by theUltimateSource
add context detail

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the problem is in your source file.

If you want to synthesize your design you have to fix:

  • A LUT 'cnt2_i_2' is driving clock pin of 11 registers.
  • Number of unplaced terminals (64) is greater than number of available sites (50)

otherwise it will only work in simulation.

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2 minutes ago, theUltimateSource said:

the problem is in your source file.

If you want to synthesize your design you have to fix:

  • A LUT 'cnt2_i_2' is driving clock pin of 11 registers.
  • Number of unplaced terminals (64) is greater than number of available sites (50)

otherwise it will only work in simulation.

YES i know but i can't figure out how to declare the 32 bit inputs so i can link them to the axi slave registers without vivado trying to place them to ports

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did you use Vivado/Tools/create and package new IP as a starting point? It generates the axi wrapper for you. Instantiate your module and connect registers to axi.

 

Again, your error log let's me assume something is wrong with your module.

Edited by theUltimateSource

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2 minutes ago, theUltimateSource said:

did you use Vivado/Tools/create and package new IP as a starting point? It generates the axi wrapper for you. Instantiate your module and connect registers to axi.

 

Again, your error log let's me assume something is wrong with your module.

thank you for replying 

editing the axi lite requires declaring the module with its inputs and linking the inputs to the slave registers ( i'm I wrong ???), so before doing that i need to get my module to work, the problem is i need two 32 inputs to my module so i can control the pwm up time and the pwm period, but when i declare the two inputs vivado tries to assign a physical port to each of the 64 bits and that's the problem because i don't need hardware ports to be assigned to them i just want to assign them to the slave registers

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2 minutes ago, yassinema2018 said:

vivado tries to assign a physical port to each of the 64 bits and that's the problem because i don't need hardware ports to be assigned to them

You are correct, you need to declare your module entity, instantiate the module, instantiate the axi interface and map the signals to your port lists. 

I think these instructions here show you exactly what you are trying to do. It uses 4 PWM signals instead of one but is very easy to adjust. 

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7 minutes ago, theUltimateSource said:

You are correct, you need to declare your module entity, instantiate the module, instantiate the axi interface and map the signals to your port lists. 

I think these instructions here show you exactly what you are trying to do. It uses 4 PWM signals instead of one but is very easy to adjust. 

is linking the 32 bits inputs the slv registers of the axi, tells vivado that no port wiring is required .?

 

thank you 

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