Error customizing/repackaging dvi2rgb IP

[tbrowning]

Good morning,

I am currently working on a project that uses the DVI2RGB IP on a custom-built PCB like the zybo-z7 board (but uses the zynq 7020 like the zed board) and would like to make my own version of the IP for several reasons but have encountered the following errors:

1) My PCB board has 2 HDMI ports configurable as sink/source, however when using 2 instances of the DVI2RGB core I get the following error: (error1.png)
 

2) I would like to make a generic data protocol around the HDMI connector that doesn't require blanking and the DVI2RGB core is a nice, open-source platform for me to experiment with new configurations. However, when repackaging the IP regardless of whether I make any changes I get the following error: (error2.png)

For 1) I know I can solve my problem by modifying the IP (and probably just by adding a top-level constraint file to overwrite the dvi2rgb.xdc file), but because of the error in 2) I cannot accomplish this task. I have searched these forums as well as Xilinx with no luck regarding this problem. I have also searched through the Xilinx documentation (UG1118) on IP packaging, but was unable to find any useful information about something I may be doing wrong. I have also tried modifying the IP every way I can think of to remove the dependency on the board.xit file, but with no luck. 

If anyone has tried this or encountered similar problems with modifying any Diligent IP your advice would be greatly appreciated!

Just to reiterate, I only really care about being able to repackage the dvi2rgb core myself, and the error above appears simply from editing the IP in the IP packager, leaving everything set as its default and repacking it. The first time I open the IP there is no implementation file group and the file utils/board/board.xit doesn’t exist, but when I repack it I get the error and when I reopen it in the ip packager again the file is there: (ippackager.png)

Some info on my setup:
I am running windows 10 64 bit, using vivado 2017.1 and have tried this with both dvi2rgb 1.6 and 1.9. If any additional information is needed please let me know.

In the upcoming semester I will be helping mentor a group of undergraduate students on the contents of this IP, so resolving this before the semester starts would be a huge help.

Best regards,

Tyler Browning

 

[jpeyron]

Hi @tbrowning,

I have reached out to more experienced engineers about this thread.

thank you,

Jon

[elodg]

Hello @tbrowning,

Error 1 is due to the fact that each dvi2rgb instantiates its own IDELAYCTRL, which really aren't that many of in the FPGA. The solution would be what Xilinx IP do, having an option for instantiating shared logic externally. Or having an IP customization option for instantiating IDELAYCTRL.

If you do implement that, please contribute back.

Error 2 must be some new Vivado sh!@$$&#&$. I have not seen this in earlier versions. Maybe try creating a new IP and importing sources.

[tbrowning]

10 hours ago, elodg said:

Hello @tbrowning,

Error 1 is due to the fact that each dvi2rgb instantiates its own IDELAYCTRL, which really aren't that many of in the FPGA. The solution would be what Xilinx IP do, having an option for instantiating shared logic externally. Or having an IP customization option for instantiating IDELAYCTRL.

If you do implement that, please contribute back.

Error 2 must be some new Vivado sh!@$$&#&$. I have not seen this in earlier versions. Maybe try creating a new IP and importing sources.

Hello @elodg

Thank you for the suggestion, I spent this morning/afternoon attempting to recreate the IP from the source files, but unfortunately ended with the same result... Once I get to the review and package stage and I re-package the IP I can see in the windows file explorer that there is a new utils folder created in the IPs directory containing the board.xit file leading to this error. I am not sure what to try next at this point.

Can anyone confirm that they see the same behavior when repacking the dvi2rgb core?

[tbrowning]

On 1/29/2018 at 4:32 PM, jpeyron said:

Hi @tbrowning,

I have reached out to more experienced engineers about this thread.

thank you,

Jon

Hello @jpeyron,

Would it be possible to have someone else revisit this topic? I tried @elodg suggestion with no luck, but I have a group of students who will try the same thing with multiple versions of Vivado to see if we can find one that works. I'm not sure what other options we have at this point

[elodg]

I just opened a project originally created in 2016.4 in Vivado 2017.4, updated all the IP, edited dvi2rgb by adding whitespace to one of the files, repackaged the IP, upgraded the IP in block design and successfully built it. Functional test passes too. Editing the IP the second time still does not show the xit file you mentioned.

Are you getting error messages related to board definition files? I needed to created a Vivado_init.tcl with path to our vivado-boards repo so that I wouldn't get errors related to board interfaces.

[tbrowning]

6 hours ago, elodg said:

I just opened a project originally created in 2016.4 in Vivado 2017.4, updated all the IP, edited dvi2rgb by adding whitespace to one of the files, repackaged the IP, upgraded the IP in block design and successfully built it. Functional test passes too. Editing the IP the second time still does not show the xit file you mentioned.

Are you getting error messages related to board definition files? I needed to created a Vivado_init.tcl with path to our vivado-boards repo so that I wouldn't get errors related to board interfaces.

 

Thank you for trying this out @elodg, currently the only messages I get are for the board.xit file where it can't read the f_xdc variable. I have the board files installed locally so I'm not sure if it is related to the board definition files, but if you could provide the tcl script I could try it, but I am not familiar with how to create such a file. I will try this setup on another machine to see if I can get different results.

[elodg]

Look for Vivado_init.tcl in:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug835-vivado-tcl-commands.pdf

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug895-vivado-system-level-design-entry.pdf