sandy Posted January 28, 2018 Share Posted January 28, 2018 I have been trying to use digilent DVI to RGB IP for zybo board, the pixel clock from the ip gives an output of 100MHz , is there any way to reduce the pixel clock frequency , if so can someone please tell me how. Link to comment Share on other sites More sharing options...
theUltimateSource Posted January 28, 2018 Share Posted January 28, 2018 The pixel clock is directly derived from the video input, TMDS CLK. One character is 10 bit. Since it is DDR your pixel clock is 5 times lower than the serial, i.e., bit clock. Link to comment Share on other sites More sharing options...
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sandy
I have been trying to use digilent DVI to RGB IP for zybo board, the pixel clock from the ip gives an output of 100MHz , is there any way to reduce the pixel clock frequency , if so can someone please tell me how.
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