Invalid value for CLKIN1_PERIOD in PLLE2_BASE

[RedMercury]

I'm trying to write a basic module for my Cmod A7 to poke around some pins on my oscilloscope.  It seems to be impossible for me to create a PLLE2_BASE instance, I always get this error:

[Netlist 29-73] Incorrect value '83.330002' specified for property 'CLKIN1_PERIOD'. The system will either use the default value or the property value will be dropped. Verify your source files.

This is the offending piece of code:

    wire clk0;
    wire clk1;
    wire clk_fb;

    PLLE2_BASE #(
      .CLKFBOUT_MULT(2),
      .CLKFBOUT_PHASE(0.0),
      .CLKIN1_PERIOD(83.33),

      .CLKOUT0_DIVIDE(2),
      .CLKOUT0_DUTY_CYCLE(0.5),
      .CLKOUT0_PHASE(0.0),
      
      .CLKOUT1_DIVIDE(2),
      .CLKOUT1_DUTY_CYCLE(0.5),
      .CLKOUT1_PHASE(0.0)
    ) pll(
      .CLKIN1(sysclk),
      .CLKFBOUT(clk_fb),
      .CLKFBIN(clk_fb),
      .RST(btn[0]),
      .CLKOUT0(clk0),
      .CLKOUT1(clk1)
    );

 

I'm using the constraints from the master XDC on github:

# Clock signal 12 MHz
set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_14 Sch=gclk
create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {sysclk}];

Any pointers as to what I'm doing wrong?  I've tried many variations on CLKIN1_PERIOD, 83, 83.3, 83.33, 83.333.

Thanks!

[hamster]

The is from memory, and I am on a phone, so don't be surprised if it is wrong...   

The PLL and the MMCM blocks have different max/min clock frequencies. 

I am pretty sure you will need to use the MMCM. 

CAn you check the datasheet and add an update to this post?

  "Artix 7 switching characteristics" should find it the correct PDF file quickly.

[RedMercury]

I’ll have a go tomorrow, but looking at the doc now PLL has a minimum frequency of 19Mhz, MMCM has a minimum frequency of 10Mhz.  Sounds like that was the problem!

Vivado could be a little more descriptive in its error messages..

[xc6lx45]

I think Hamster is right. I had to use MMCM for a 12 MHz crystal, PLL doesn't work.

The easiest way to fix this is in Vivado, Flow navigator window on the left under "Project manager": "IP Catalog".

Enter "clk" into the search window, pick "Clocking wizard" under "FGPA features and clocking", "clocking".

Select "Primitive": MMCM (should be default), enter "Primary input clock": 12 (Megahertz). Set the output frequency, disable unused inputs and outputs such as reset (fewer warnings later) and click "generate".

The "component name" on the top, e.g. "clk_wiz_0", is used for instantiation.

Oh, and you should probably comment out the "create_clock" line in the constraints file, because the frequencies are now set by the clocking IP. Otherwise Vivado will start analyzing interactions between "alternative" clocks that don't exist.