Aurora_TX and RX Loopback Test result Fail Options

[Thausikan]

Hi,

 I have integrated simplex TX aurora block and simplex RX aurora blocks into a single design through a loop-back in order to make duplex mode. But while simulating the XSDK codes, TX length and RX length are mismatched.

I am working with Kintex development DAQ board [xc7k160tffg676-2], and i have attached the BD design in which TX and RX are make into external. Where i am going wrong i don`t know, please point out and guide me.

Please find the attachment of BD diagram.
 

Thanks

[JColvin]

Hello @Thausikan,

Unfortunately, the Digilent engineers on the Forum have limited experience with the Aurora IP and have not used the Kintex board that you have referenced. You will likely receive some better information by contacting Xilinx or the manufacturer of your board.

Thank you,
JColvin