XADC conversion rate

[cristian_zanetti]

good day to all, my question is this:

I am using the XADC of the Nexys 4 DDR, using the single channel mode, I want to sample at 1000 KSPS but using the IP CORE XADC Wizard it tells me that with these features the current conversion rate decreases to 961540 KSPS, I have searched the documentation of the XADC but I can not find a concrete answer to why this happens.

If someone could help me, I would appreciate it.

[JColvin]

Hello @cristian_zanetti,

It depends on how your design is set up since Vivado will work on optimizing and potentially changing parameters to make sure the sampling rate works. Can you provide screenshots of your xadc settings and your block design?

Thanks,
JColvin

[cristian_zanetti]

 

VHDL

[jpeyron]

Hi @cristian_zanetti,

I am not seeing anything specifically about your configuration that would cause this. Have you tried changing your averaging configuration?  I would alter the xadc configurations until i found the setting that is affecting the performance. I would also look at this demo as a basic reference for setup. 

thank you,

Jon

[xc6lx45]

I think the ADC requires 26 cycles per conversion, kind of an odd number.
If you feed it an input clock of 104 MHz, it will give exactly 1 MSPS (according to my XADC wizard on Artix 7) with an internal clock divider of 4 (26*4=104).

BTW, your register printout seems to show a clock divider of 25 (0x19?? in register 42), so I guess this will run much slower?

 

[cristian_zanetti]

1.

Hace 7 horas, xc6lx45 dijo:

Creo que el ADC requiere 26 ciclos por conversión, una especie de número impar.
Si el tiempo de espera es de 104 MHz, exactamente 1 MSPS (de acuerdo con mi asistente XADC en Artix 7) con un divisor de reloj interno de 4 (26 * 4 = 104).

Por cierto, su impresión de registro parece mostrar un divisor de reloj de 25 (0x19? En el registro 42), así que supongo que esto es mucho más lento?

 

all part of this, I do not know what equation IP CORE applies, I do not know why it decreases the sampling frequency

[Piasa]

You want to use an MMCM or clocking IP core of some form in order to get a 104MHz clock that can be used to get 1000MSPS vs 25/26ths that rate.