AD1 - SDK - FDwfAnalogInFrequencySet can be 0.1 sps to 100 Msps

[markb82]

Hi,

I've been using the AD1 and the Waveforms SDK, and it looks like you can specify any sampling rate from 0.1sps to 100Msps (double precision value to FDwfAnalogInFrequencySet).  Does anyone know how this is accomplished?

I'm curious if the ADF4390 PLL which is generating the 200 MHz clock for the ADC is 'reprogrammed' to the nearest integer multiple of the requested frequency which sets it close to 200 MHz, f_PLL = 2*fs*round(100 Msps / fs)?  And then the FPGA simply decimates the samples by the integer multiple (round(100Msps/fs))?

Or is the ADC sampling rate fixed at 100 Msps (200MHz clock), and some sort of multirate filter is used to re-sample the samples in the FPGA?

Or is it something else?

If the PLL frequency is slightly adjusted, and the same PLL is used for the DAC to generate a waveform (such as a DDS sine wave), then the DDS must be adjusted for the new reference frequency?

I'm running into a couple issues trying to create my own Bode analyser script.

Thanks,

Mark

 

[attila]

Hi @markb82

The ADC is always running a 100Msps. 
With FDwfAnalogInFrequencySet you can configure an integer division (N) of 100MHz.
For each channel with FDwfAnalogInChannelFilterSet you can choose how the ADC samples get stored: Decimate (Nth 100MHz ADC conversion), Average (average of N conversions), or Min/Max.

[markb82]

Thank you Attila.  That jogged my memory from when I used the AD1 originally a few years ago.  I did not know about the option to average or min/max the samples.

You can call FDwfAnalogInFrequencyGet and see the actual sample-rate after you've set it, and it will be an integer division of 100MHz.