bahare Posted August 18, 2015 Share Posted August 18, 2015 i work whit pmod that producted whit maxim company , maxim company get me a file project for pmods in this link http://content.maximintegrated.com/en/design/tools/applications/evkit-software/index.mvp/id/1064 but in this project every pmod port on zedboard luanch alone , i want two port pmod work together can you help me ?? Link to comment Share on other sites More sharing options...
Alex Posted August 19, 2015 Share Posted August 19, 2015 Hi, it looks like we need to login to get the materials. What do you mean by two port Pmods? Link to comment Share on other sites More sharing options...
bahare Posted August 19, 2015 Author Share Posted August 19, 2015 i want setting up ADC and DAC Peripheral Module at the same time on JA and JB on zedboard . maxim's project file is for 15 Peripheral Module that every time just one pmod can use, can you help me that how do i change maxim's ready project file that ADC and DAC setting up whit together at the same time ? Link to comment Share on other sites More sharing options...
Alex Posted August 20, 2015 Share Posted August 20, 2015 Hi, thanks for the information. So, you want to do a loopback from AD to DA through ZED? Link to comment Share on other sites More sharing options...
bahare Posted August 20, 2015 Author Share Posted August 20, 2015 Hi Alex yes , exactly. Link to comment Share on other sites More sharing options...
bahare Posted August 21, 2015 Author Share Posted August 21, 2015 can you help me Alex?? Link to comment Share on other sites More sharing options...
Alex Posted August 21, 2015 Share Posted August 21, 2015 Hi, actually, there is a reference design on VHDL for the loopbcak. It is target on the Nexys 3 and Digilent Pmod ADC and DAC. You can borrow the design to apply that to yours. If you are using Vivado, you can ignore the statement "requires a ChipScope Pro license to synthesize the project." http://www.digilentinc.com/Data/Documents/Demonstration Project/PmodAD2_DA1_CSE_Demo.zip This zip file contains a Xilinx ISE demo project for the PmodAD2 and a PmodDA1. This project was made for Xilinx ISE 13.4, targets the Nexys3, and is written in VHDL. It requires a ChipScope Pro license to synthesize the project. Hope this helps Link to comment Share on other sites More sharing options...
bahare Posted August 22, 2015 Author Share Posted August 22, 2015 hi thanks alot , Do you think I can change the following codes in sdk setting up two pmod port JA and JB at the same time? void increment_active_PMOD_Port()/*** \brief Increments the Active PMOD port and sets the globals UART, SPI, I2C, GPIO peripheral settings** \retval None*/{ g_nActivePMODPort++; if(g_nActivePMODPort>3) g_nActivePMODPort=0; switch(g_nActivePMODPort) { case 0: g_unActivePeripheralAddressI2C =XPAR_IIC_0_BASEADDR; g_unActivePeripheralAddressSPI =XPAR_SPI_0_BASEADDR; g_unActivePeripheralAddressUart =XPAR_AXI_UARTLITE_0_BASEADDR; g_pActiveGPIOPort =&g_xGpioPmodPortA; break, case 1: g_unActivePeripheralAddressI2C =XPAR_IIC_0_BASEADDR; g_unActivePeripheralAddressSPI =XPAR_SPI_0_BASEADDR; g_unActivePeripheralAddressUart =XPAR_AXI_UARTLITE_0_BASEADDR; g_pActiveGPIOPort =&g_xGpioPmodPortA; g_unActivePeripheralAddressI2C =XPAR_IIC_1_BASEADDR; g_unActivePeripheralAddressSPI =XPAR_SPI_1_BASEADDR; g_unActivePeripheralAddressUart =XPAR_AXI_UARTLITE_1_BASEADDR; g_pActiveGPIOPort =&g_xGpioPmodPortB; break; case 2: g_unActivePeripheralAddressI2C =XPAR_IIC_2_BASEADDR; g_unActivePeripheralAddressSPI =XPAR_SPI_2_BASEADDR; g_unActivePeripheralAddressUart =XPAR_AXI_UARTLITE_2_BASEADDR; g_pActiveGPIOPort =&g_xGpioPmodPortC; break; case 3: g_unActivePeripheralAddressI2C =XPAR_IIC_3_BASEADDR; g_unActivePeripheralAddressSPI =XPAR_SPI_3_BASEADDR; g_unActivePeripheralAddressUart =XPAR_AXI_UARTLITE_3_BASEADDR; g_pActiveGPIOPort =&g_xGpioPmodPortD; break; default: g_nActivePMODPort=0; g_unActivePeripheralAddressI2C =XPAR_IIC_0_BASEADDR; g_unActivePeripheralAddressSPI =XPAR_SPI_0_BASEADDR; g_unActivePeripheralAddressUart =XPAR_AXI_UARTLITE_0_BASEADDR; g_pActiveGPIOPort =&g_xGpioPmodPortA; break; }} void max_set_PMOD_port(int nPortNumber, u8 uchPortType) { if(nPortNumber>=0 && nPortNumber<=3) { g_auchPortType[nPortNumber]=uchPortType; } max_configure_PMOD_port(g_auchPortType[0],g_auchPortType[1],g_auchPortType[2],g_auchPortType[3]); delay(ABOUT_ONE_SECOND / 10);} void max_configure_PMOD_port(u8 uchPmodPortA, u8 uchPmodPortB, u8 uchPmodPortC, u8 uchPmodPortD){ u8 uchPmodPortSelectBits=0; // The PMOD ports are configured with an 8 bit word sent to GPIO2 // Bits 1:0 are for port #A // Bits 3:2 are for port #B // Bits 5:4 are for port #C // Bits 7:6 are for Port #D //S = 2'b00 => UART active (PMOD_PORT_TYPE_UART) //S= 2'b01 => SPI active (PMOD_PORT_TYPE_SPI) //S = 2'b10 => GPIO active (PMOD_PORT_TYPE_GPIO) //S = 2'b11 => I2C active (PMOD_PORT_TYPE_I2C) uchPmodPortSelectBits = (uchPmodPortD << 6) + (uchPmodPortC << 4) + (uchPmodPortB << 2) + uchPmodPortA; XGpio_DiscreteWrite(&g_xGpioPmodPortMuxIO, 1, uchPmodPortSelectBits);} Link to comment Share on other sites More sharing options...
Alex Posted August 29, 2015 Share Posted August 29, 2015 Hi, unfortunately, I am not familiar with the SDK in Vivado. By glancing through your C codes, I guess it is doable. Perhaps, you should look at the SDK tutorial at Xilinx. Link to comment Share on other sites More sharing options...
bahare Posted August 29, 2015 Author Share Posted August 29, 2015 hi thanks alot Alex Link to comment Share on other sites More sharing options...
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i work whit pmod that producted whit maxim company , maxim company get me a file project for pmods in this link http://content.maximintegrated.com/en/design/tools/applications/evkit-software/index.mvp/id/1064 but in this project every pmod port on zedboard luanch alone , i want two port pmod work together can you help me ??
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