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alex121

connecting two 6pin pmods to 12pin connector in IP-Integrator

Question

Hey guys,

i got two Pmod AD1 and I would like to get them to work using a single 12 pin connector on my nexys video.
I'm using the IP-Integrator/Block Design and the Pmod AD1 IP-Core. (Works great with single Pmod)
Can someone give me a hint how to make the connections in the Block Design?

Thanks you
Alex

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Hi @Mahdi,

You should open the pmod out and make the pin 1-4 t external for both pmod gps and rtcc. I have attached a screen shot of my block design.and xdc which generated a bitstream. 

# Pmod Header JA
set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports { Pmod_GPS_JA1 }]; #IO_L17P_T2_34 Sch=JA1_P
set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS33 } [get_ports { Pmod_GPS_JA2 }]; #IO_L17N_T2_34 Sch=JA1_N
set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { Pmod_GPS_JA3  }]; #IO_L7P_T1_34 Sch=JA2_P
set_property -dict { PACKAGE_PIN Y17   IOSTANDARD LVCMOS33 } [get_ports { Pmod_GPS_JA4 }]; #IO_L7N_T1_34 Sch=JA2_N
set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { Pmod_RTCC_JA7 }]; #IO_L12P_T1_MRCC_34 Sch=JA3_P
set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports { Pmod_RTCC_JA8 }]; #IO_L12N_T1_MRCC_34 Sch=JA3_N
set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { Pmod_RTCC_JA9}]; #IO_L22P_T3_34 Sch=JA4_P
set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { Pmod_RTCC_JA10 }]; #IO_L22N_T3_34 Sch=JA4_N

you will get warning about not using the other pins but do not worry about these.

thank you,

Jon
 

pmod_gps_rtcc_same_pmod_port.jpg

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Hi @Mahdi,

Under the boards tab you right click on I2C on J2 and choose iic. You do not need to add an xdc. Then in sdk you add the PmodRTCC.c and PmodRTTC.h in the scr folder with your main file in the created application. 

thank you,

Jon

Arty_z7_rtcc_2.jpg

Arty_z7_rtcc.jpg

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Hi @alex121

Instead of connecting to a pmod port like ja or jb right click on the pmod out of the ip core and make external for both Pmod AD1 IP cores. Then after you have created a wrapper use an xdc file to constrain the pins named for the 2 pmod AD1 IP cores. The generate a bitstream and export to sdk. Once in sdk you will need to alter the main.c of the AD1 to instantiate two different AD1 IP cores Like below:

PmodAD1 myDevice;

PmodAD1 myDevice2;

You will also need to call AD1_begin twice.like below:

 AD1_begin(&myDevice, XPAR_PMODAD1_0_AXI_LITE_SAMPLE_BASEADDR);

AD1_begin(&myDevice2, XPAR_PMODAD1_1_AXI_LITE_SAMPLE_BASEADDR);

in the demo run function you will need to call the different function for both instantiations myDevice and myDevice2.

Cheers,

Jon

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Hi @jpeyron

I have a follow-up question on this subject. I am trying to do the same sort of experiment with a PmodGPS and a PmodRTCC. I was able to create the wrapper and import the XDC file, but I am not sure exactly how to use it to constrain the pins for these 2 Pmods. To be clear, I can see in the XDC file that all of the lines for the Pmod ports are commented out, but should I just comment them back in or should I find out the name of the pins that are associated with the Pmods and put those pin names into get_ports functions of XDC file? Here is the JA header part of XDC file.

## Pmod Header JA
#set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L17P_T2_34 Sch=JA1_P
#set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L17N_T2_34 Sch=JA1_N
#set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L7P_T1_34 Sch=JA2_P
#set_property -dict { PACKAGE_PIN Y17   IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L7N_T1_34 Sch=JA2_N
#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L12P_T1_MRCC_34 Sch=JA3_P
#set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L12N_T1_MRCC_34 Sch=JA3_N
#set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { ja_p[4] }]; #IO_L22P_T3_34 Sch=JA4_P
#set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { ja_n[4] }]; #IO_L22N_T3_34 Sch=JA4_N

How does Vivado recognize that the external connections we made for the Pmods should be connected to ja or jb? Every time I click on those external connections, it opens up about 24 pins and it is not easy to differentiate between them. I really appreciate your response.

Thanks,

Mahdi

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Hi @Mahdi,

If you are using the board files and connecting the project using the ip cores by connecting them to the design using the pmod ports like ja, jb, jc then vivado handles the hardware connections and you will not need to use an xdc.

thank you,

Jon

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Hi @jpeyron

I believe there has been a misinterpretation. I am already aware of how to use each Pmod in Vivado. I am trying to connect 3 Pmods (NAV, GPS and RTCC) to Arty-Z7-10 board, while that board has only 2 ports available (ja, jb). I decided to split ja between GPS and RTCC using a splitter cable (since both use one row of port), and connect PmodNAV to jb. I followed your instruction above until creating the wrapper, but I guess GPS and RTCC pmods are not actually connected to the ja, and they are still external connection. When I am clicking on the Connector JA on the boards tab, it only allows me to attach one Pmod to it. I have uploaded my block design. How does Vivado realize that it should connect these 2 Pmods to ja? I generated the bitstream and it was fine, but I do not think I would be able to access the output of those 2 Pmods in SDK software. I tried to constrain the pins using XDC file, and that is where I faced my earlier question. 

Thanks,

Mahdi

1.thumb.png.c9ed5f6a3d0dd0d14e6427a417c2845b.png

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Hi @Mahdi,

Sorry about the misunderstanding. To use the top row for one pmod and the bottom for the other right click on the pmod out of both ip cores  and select make external. Then you generate a wrapper and look at the pin names in the wrapper to change in the xdc for ja. I would change the pmod_out_1 and 0 to something a little more different to better recognize the pins names in the wrapper. Once you have made the wrapper post it to the thread and the updated block design if you change the pmod_out_0 and 1.  i can help you make the xdc if you would like.

thank you,

Jon

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Thanks @jpeyron for your quick response. I really appreciate if you would help me to make the correct xdc file for this project. I have attached both the block design and wrapper file. In this block design, PmodNAV is already linked to the port jb (which I renamed to NAV_out). Now, I am trying to link PmodGPS and PmodRTCC to the top and bottom row of port ja. As you can see, the connector JA is not taken yet. The default XDC file of the Art-Z7-10 is also attached.

-Mahdi

Block_design.thumb.png.08d714158a67f1922824dc1f7b8be127.png

Arty-Z7-10-Master.xdc

design_1_wrapper.v

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Hello @jpeyron

By following your response on this post, I have almost figured out how to modify the XDC file using the board schematics, but I have one concern. When I am looking at JA header definition in the XDC file, there are 8 lines of code as following. The first 4 lines are for the top row of pmod port, and the rest are for the bottom row. 

## Pmod Header JA
#set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L17P_T2_34 Sch=JA1_P
#set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L17N_T2_34 Sch=JA1_N
#set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L7P_T1_34 Sch=JA2_P
#set_property -dict { PACKAGE_PIN Y17   IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L7N_T1_34 Sch=JA2_N
#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L12P_T1_MRCC_34 Sch=JA3_P
#set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L12N_T1_MRCC_34 Sch=JA3_N
#set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { ja_p[4] }]; #IO_L22P_T3_34 Sch=JA4_P
#set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { ja_n[4] }]; #IO_L22N_T3_34 Sch=JA4_N
 

I am also looking at the wrapper file, and there are about 16 inout definition for the 2 pmods that I am going to use as following:

  inout GPS_out_pin10_io;
  inout GPS_out_pin1_io;
  inout GPS_out_pin2_io;
  inout GPS_out_pin3_io;
  inout GPS_out_pin4_io;
  inout GPS_out_pin7_io;
  inout GPS_out_pin8_io;
  inout GPS_out_pin9_io;
  inout RTCC_out_pin10_io;
  inout RTCC_out_pin1_io;
  inout RTCC_out_pin2_io;
  inout RTCC_out_pin3_io;
  inout RTCC_out_pin4_io;
  inout RTCC_out_pin7_io;
  inout RTCC_out_pin8_io;
  inout RTCC_out_pin9_io;

I know that these pins should be called in the get_ports functions of XDC file, but how am I supposed to accommodate 16 pins names in only 8 get_ports function? Should I only use pin number 1 to 4 or 7 to 10 or something else?

Thanks again,

-Mahdi

 

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Hi @Mahdi,

I believe you should use the 

#set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports {   GPS_out_pin1_io}]; #IO_L17P_T2_34 Sch=JA1_P
#set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS33 } [get_ports {GPS_out_pin2_io }]; #IO_L17N_T2_34 Sch=JA1_N
#set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { jGPS_out_pin3_io }]; #IO_L7P_T1_34 Sch=JA2_P
#set_property -dict { PACKAGE_PIN Y17   IOSTANDARD LVCMOS33 } [get_ports { GPS_out_pin4_io}]; #IO_L7N_T1_34 Sch=JA2_N
#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports {RTCC_out_pin1_io }]; #IO_L12P_T1_MRCC_34 Sch=JA3_P
#set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports { RTCC_out_pin2_io}]; #IO_L12N_T1_MRCC_34 Sch=JA3_N
#set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { RTCC_out_pin3_io}]; #IO_L22P_T3_34 Sch=JA4_P
#set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { RTCC_out_pin4_io }]; #IO_L22N_T3_34 Sch=JA4_N

and then alter the pmod nav to use jb.

thank you,

Jon

 

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Hello @jpeyron

I have already tried this, and some other pin numbers combinations such as GPS_out_pin1_io to GPS_out_pin4_io and RTCC_out_pin4_io to RTCC_out_pin4_io and vice versa. But every time I am generating the bitstream, I am getting this error which says:

 

[DRC NSTD-1] Unspecified I/O Standard: 8 out of 154 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: GPS_out_pin10_io, GPS_out_pin7_io, GPS_out_pin8_io, GPS_out_pin9_io, RTCC_out_pin10_io, RTCC_out_pin7_io, RTCC_out_pin8_io, and RTCC_out_pin9_io.

and 

[DRC UCIO-1] Unconstrained Logical Port: 8 out of 154 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: GPS_out_pin10_io, GPS_out_pin7_io, GPS_out_pin8_io, GPS_out_pin9_io, RTCC_out_pin10_io, RTCC_out_pin7_io, RTCC_out_pin8_io, and RTCC_out_pin9_io.

 

this error is for the one you recommended. Apparently Vivado wants us to address all of the 8 pins of each pmod individually, and leaving them behind causes this issue. How am I supposed to fix this? 

 

Thanks,

Mahdi
 

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Hello again @jpeyron

 

I guess I am still having issues with this setup. As I told you earlier, I got the bitstream generated and imported to SDK. Now, as soon as I hit the program FPGA button, the GPS led goes on and stays on forever which has no meaning to me, unless the wiring would be wrong! but I am sure that both Pmods that share the j-port are plugged in correctly. I took this outside to get a GPS lock, but did not make a difference. Neither GPS nor RTCC are working correct now, even if I just try to initialize and use one of them. My C code freezes right inside initialization of the RTCC (when I am calling RTCC_stopClock(&rtc)) which is the first Pmod I am initializing. All these are telling me we are not fully connected to these Pmods in the block design. What do you think the problem is? I have attached my block design, wrapper file, and the C code. Here is my XDC file as well.

## Pmod Header JA
set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports Pmod_GPS_JA1]
set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports Pmod_GPS_JA2]
set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports Pmod_GPS_JA3]
set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33} [get_ports Pmod_GPS_JA4]
set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports Pmod_RTCC_JA7]
set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports Pmod_RTCC_JA8]
set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS33} [get_ports Pmod_RTCC_JA9]
set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports Pmod_RTCC_JA10]

 

I did not do anything fancy. I am getting RTCC, GPS and NAV data in a loop and print them to terminal. I should also mention that this c code worked fine with when I only had GPS and NAV in my block design, and as soon as I added RTCC with your method, it stopped working. 

Thanks,

Mahdi

design_1_wrapper.v

Block_design.png

main.cc

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Hi @Mahdi,

I do not see anything directly wrong with your design or sdk code. Tomorrow I will try to trouble shoot your sdk code using an arty z7 10 and the different pmods.  Are you able to get just the Pmod RTCC working by itself using your C code?

thank you,

Jon

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Hi @jpeyron

If I connect each of the Pmods to ja port individually and not make the connections external and follow the normal procedure for making the block design (such as connecting the Pmod to ja port via sources tab of Vivado), I can see the correct output in the terminal with the same SDK code I sent you (of course you need to comment out the other Pmods code), but if I try to modify the wrapper file and XDC file manually the way you said, I can not connect to neither of the Pmods, which makes me think none of the pmods that are sharing a port could be even initialized by this method.

If you look at the wrapper file, the PmodGPS and PmodRTCC pins are defined as output (which are sharing ja port) in the module, while the PmodNAV which is taking jb port in declared as inout. I thought this might cause the issue, so I changed the GPS and RTCC pins to inout, but that did not solve the problem either. I hope you can figure this out.

Thanks,

-Mahdi

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Hi @Mahdi,

It is definitely something to do with the rtcc code. I am able to run the nav and gps code if i comment out the rtcc code. /i was not even able to get into the initialize function. I will look further into this code tomorrow.

thank you,

Jon

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Hi @jpeyron

I am not sure if you used the XDC and SDK code I gave you, but my problem right now is far beyond the c code. As soon as I hit the program FPGA button in either Vivado or SDK software, the GPS light goes on, and never turns off again, which makes me think the problem is with the bitstream. Didn't you experience such problem? The C code is the next step which we should be worried about. I am %100 sure that the attached C code is working fine, when there is only one Pmod connected to ja port in block design. Problem starts when we try to communicate with 2 pmods through one port. One thing I noticed is that all 6 pins on the top and bottom row of each J-port are electrically connected. I understand that GND and VCC could be shared, but why are the other 4 pins connected? Couldn't such connection mess up the whole splitting of the port?

I am working on a project which is very close to its deadline, and the only part that is not cooperating is this port splitting. I realized that there is also a I2C port (J2) on the Arty-Z7-10 which can be used to access devices such as PmodRTCC. Do you think it is doable to connect the PmodRTCC to that port and communicate with it directly? If I do this, can I still use the PmodRTCC.h library? I am not very optimistic that we can get GPS and RTCC both working on one J-port. 

Thanks

-Mahdi

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Hi @Mahdi,

On Friday I looked closer to the output when i had commented out the rtcc code and the gps output is garble. So i ended up spending time looking into that issue to not avail.  Are you using the adruino/chipkit header? If not we can connect one of the pmods to the Header and use JA and JB for just one pmod. 

thank you,

Jon

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Hi @jpeyron

I believe that is the way to go. I have occupied almost all of the GPIO pins on the Arduino header, but still the Chipkit I2C is available which I guess it is the following lines in the XDC file:

## ChipKit I2C
#set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_34 Sch=CK_SCL
#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_34 Sch=CK_SDA

I can easily connect my PmodRTCC to these two ports physically, but how am I supposed to communicate with it in my C code? It was easy to run the PmodRTCC example code while it was connected to ja port, but I have no idea how to talk to it when it is connected to SCL and SCA on the Chipkit. Could you please help me on this part?

 

Thanks,

Mahdi

 

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Posted (edited)

Hi @jpeyron  , @Mahdi , @alex121, @D@n

I completed my block diagram design in Vivado, and I used Microblaze IP for AXI control, and PmodDA3 IP.  (1st picture)

But , I want to know how to assign Constraints to the JD Connector and what are source code that should be written in SDK ? 

I am using Arty 7. 

Kindly, see the attached pictures.

Looking forward your help.

Thanks .

design_completed.JPG

photo_2018-12-22_00-55-08.jpg

Edited by Ahmed Alfadhel

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