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anitaG

Arty-Z7 XADCDemo does not synthesize under vivado 2017.4

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Hello,

Got ARTY-Z7 and trying to load first working project in Vivado. Actually there is no other choice but XADCdemo. Took latest bundle from GIT and  followed instructions here:

https://reference.digilentinc.com/learn/programmable-logic/tutorials/github-demos/start

All was as expected till "3. Generate Bitstream" section. The synthesis failed with error "

[Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified

Anybody experienced could point what was wrong and how to fix it?

Screen attached.

 

 

 

 

screen.png

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Hi @anitaG,

I ran the project on 2017.4 and it successfully generated a bitstream for me.

We don't have a set way to verify if the project was correctly imported; what I would probably recommend is to look to see if you can upgrade the XADC IP that comes with Vivado (go to Tools>Report>Report IP Status) and then see if the xadc_wiz_0 IP can be upgraded and try re-running the project. Otherwise, I would probably delete the project from your computer and then re-download it from our GitHub.

Let me know how this goes.

Thanks,
JColvin

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Hello @anitaG,

I don't have 2017.4 installed quite yet, but which release are you using from GitHub (link)? My understanding is that you'll need the -3 version at the top of the page rather than the -2 version to make sure the sources are correctly imported, since that is what I needed to do for 2016.4 for this particular project to successfully generate a bitstream.

Thank you,
JColvin

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yes, it is latest "-3" version

55 minutes ago, JColvin said:

make sure the sources are correctly imported

how to verify if they are corectly imported or not? Up to the point all was as per instructions, no other errors.

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