I've done the initial design of a register file (16x 32-bit registers, two write ports, four read ports) in VHDL as part of a larger project, but seeing as I am a relative newcomer to HDLs, I was hoping to get some feedback on my design, any errors I may have made, or any improvements I might want to make.
Here is the VHDL:
-- Register file
-- Two write ports, four read ports.
-- For performance reasons, this register file does not check for the same
-- register being written on both write ports in the same cycle. CPU control
-- circuitry is responsible for preventing this condition from happening.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.cpu1_globals_1.all;
use work.func_pkg.all;
entity registerFile is
port
(
clk : in std_logic;
rst : in std_logic;
writeEnableA : in std_logic;
writeEnableB : in std_logic;
readSelA, readSelB, readSelC, readSelD, writeSelA, writeSelB : in std_logic_vector(3 downto 0);
data_inA, data_inB : in std_logic_vector(DATA_WIDTH - 1 downto 0);
data_outA, data_outB, data_outC, data_outD : out std_logic_vector(DATA_WIDTH - 1 downto 0)
);
end registerFile;
architecture behavioral of registerFile is
type regArray is array (0 to 15) of std_logic_vector(DATA_WIDTH - 1 downto 0);
signal registers : regArray := (others => (others => '0'));
begin
data_outA <= registers(to_integer(unsigned(readSelA)));
data_outB <= registers(to_integer(unsigned(readSelB)));
data_outC <= registers(to_integer(unsigned(readSelC)));
data_outD <= registers(to_integer(unsigned(readSelD)));
registerFile_main : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
registers <= (others => (others => '0'));
else
if(writeEnableA = '1') then
registers(to_integer(unsigned(writeSelA))) <= data_inA;
end if;
if(writeEnableB = '1') then
registers(to_integer(unsigned(writeSelB))) <= data_inB;
end if;
end if;
end if;
end process;
end behavioral;
This design is intended for use on FPGAs, hence the use of default values for the registers.
Question
CurtP
Hey everyone,
I've done the initial design of a register file (16x 32-bit registers, two write ports, four read ports) in VHDL as part of a larger project, but seeing as I am a relative newcomer to HDLs, I was hoping to get some feedback on my design, any errors I may have made, or any improvements I might want to make.
Here is the VHDL:
This design is intended for use on FPGAs, hence the use of default values for the registers.
I appreciate any feedback you might have!
Thanks,
- Curt
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