TTL Inputs

[CH]

I have a Nexys4 Board equipped with the ARTIX 7 FPGA. I am attempting to input two 3.3V TTL signals (clock and data) from an external source into the FPGA via the PMOD connectors. It is not working and I believe the problem is the presence of the 200-ohm series resistors on all the lines connecting the PMOD connectors to the FPGA: most of the 3.3 V is dropped across the series resistor so that the voltage seen by the FPGA is too small to be registered as ones and zeros. Are there any recommendations on how to correct this?

[hamster]

Hi Ch,

You shouldn't be having this problem, unless the pin you are connecting your signal to is configured to act as output rather than an input. 

When configured as input then almost no current should flow thorough the resistor - maybe a mA at most, and flowing through a 200 ohm resistor should only drop 0.2V per mA. Can you double-check that the pin has been correctly assigned in your constraints file?

I always get the top and bottom rows of the PMOD mixed up - the upper row is pins 1 through 4 and the lower row is 5 to 8 (or 0 through 3 on top and 4 through 7, on bottom, if you start counting at zero).

Remember to post back and let us all know if you solved the problem!

Mike

[CH]

Hi Mike,

Thanks for getting back so quickly. Up until this moment I didn't know that you could change the pins in the constraint file (I've only taken one FPGA class). I simply used the master Nexys 4 UCF file that was provided by Digilent and uncommented the pins I needed. How do you change the pins to be input pins from the UCF?

I have included the section of the UCF containing the pins I need. The nets are "clk" and "data_in". I must confess that originally I did not have the line NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;  but when I ran the code with out it I got an error. It told me I could suppress it to be a warning with that line so I did.

## Pmod Header JC
NET "clk"                LOC = "K2"    | IOSTANDARD = "LVCMOS33";        #Bank = 35, Pin name = IO_L23P_T3_35,                        Sch name = JC1
NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;  
#NET "JC<1>"            LOC = "E7"    | IOSTANDARD = "LVCMOS33";        #Bank = 35, Pin name = IO_L6P_T0_35,                        Sch name = JC2
#NET "JC<2>"            LOC = "J3"    | IOSTANDARD = "LVCMOS33";        #Bank = 35, Pin name = IO_L22P_T3_35,                        Sch name = JC3
#NET "JC<3>"            LOC = "J4"    | IOSTANDARD = "LVCMOS33";        #Bank = 35, Pin name = IO_L21P_T3_DQS_35,                    Sch name = JC4
NET "data_in"            LOC = "K1"    | IOSTANDARD = "LVCMOS33";        #Bank = 35, Pin name = IO_L23N_T3_35,                        Sch name = JC7
#NET "JC<5>"            LOC = "E6"    | IOSTANDARD = "LVCMOS33";        #Bank = 35, Pin name = IO_L5P_T0_AD13P_35,                    Sch name = JC8
#NET "JC<6>"            LOC = "J2"    | IOSTANDARD = "LVCMOS33";        #Bank = 35, Pin name = IO_L22N_T3_35,                        Sch name = JC9
#NET "JC<7>"            LOC = "G6"    | IOSTANDARD = "LVCMOS33";        #Bank = 35, Pin name = IO_L19P_T3_35,   

[hamster]

That looks fine, Humm. So you are using the rightmost-pin from on the bottom row of JC (JC1 is at the top of the right end).

How the pin is configured (input/output) It depends on the top level design.  What does your top level VHDL or Verilog file look like?