Having trouble with CMod S6

[Tom Lum]

I am a teacher for Project Lead the Way and my course is Digital Electronics.  In the course we use the CMOD S6 for about half of the course.  Typically we use a program called Multisim to create circuits in what is know as PLD mode (Programmable Logic Device) and we export those programs via USB to the CMOD S6 that is attached to a specialty breadboard that can provide power, buttons, switches, etc.  My issue is that I cannot find any documentation about what each of the 48 pins can be used for.  We are told 24 and 25 are power and ground and we should use PIO14 to hook up an external clock but no reason is ever given as to why.  Some of our logic programs only work if we use higher numbered pins and not lowered numbered ones.  Some programs work with the onboard buttons, some programs can't use them.  I am sitting in a class with 20 people trying to figure these nuances out and it all guess work.  The product literature talks of multiple clock (signal voltage) outputs but not how to get them or how to change their frequency.  Can anyone point me in the correct direction?

Thanks,

Tom Lum

[Commanderfranz]

Hi Tom,

From what I understand, your biggest concern is  not knowing what each of the pins can be used for. I am going to answer that with a process that can be followed for each pin of interest. 

Say for example, you want to use an IO pin. If you open up the UCF file, you'll see a section of IO ports. For this example I will choose PORTA<0>. In the same line as the NET name, you will find the pin name. 

Next open the schematics. If you search for P5 you will find pin P5 on the schematics. From pin P5 extends a wire which goes to PIO01. This is on sheet 3 of the schematics. 

Next go to the first page of the schematics. Here you will find the DIP pin numbers in the top left corner. Look for PIO01 which connected to P5. You can see from the DIP pin diagram, that the DIP pin# is 1. 

 

If you look on the board DIP pin 1 is labeled on the opposite side as the micro USB port. 

 

So if you use IO pin PORTA<0> the physical connection is pin 1. You can use a similar procedure to find the intended use of each physical pin. 

As for the clocks, the reference manual refers to the 8MHz clock as FPGA-GCLK, this is the section this clock is in, but to use it the NET is called CLK. Same story for the 1Hz clock, except it is refered to as the CLK_LFC, and can be used as CLK_LFC.

Let me know if you have any more questions.

Kaitlyn

 

[Commanderfranz]

Hi again Tom,

I was informed that at one point there was a pin out diagram and it at some point disappeared from the reference manual. I've found it and attached it here, and will add it back to the reference manual. 

 

Kaitlyn