Instantiating Nexys4 SRAM to DDR Component

[DoctorWkt]

I'm about to play with the Nexys4 DDR "SRAM to DDR" component, but I've never used a MIG or a pre-existing netlist before. The instructions say "Components can either be inserted into a project as a pre-compiled netlist (.ngc), or as sources by copying the VHDL and MIG project files into your project." Can someone help me with an explanation on how to do this?! I'm using Vivado 2015.1. Thanks all! Warren

[TommyK]

Hi Warren,

I made a bare bones top module that includes the SRAM2DDR component. You should be able to work from here to do what you're trying to do.

 

Good luck!

Tommy

top.vhd

[TommyK]

Hi Warren,

I have never tried working with .ngc files before, but you can copy the VHDL and MIG project files by first creating a project, with the Nexys4 DDR as the target board.

• Click "Add Sources" 
• Click the add design sources bullet and click next
• Click the green plus and select add files
• Find "Ram2Ddr_RefComp/Source/Ram2DdrXadc_Ref_Comp/ram2ddrxadc.vhdl", or the other source file (ram2ddr.vhd) if you are using the XADC in your project elsewhere.
• Once this is added, go back to "Add Sources" and select add existing IP
• Navigate to the same folder as before and go into ipcore_dir/
• Select ddr.xco and click OK

This will add the VHDL component and the IP core that Mihaita created for the Nexys4 DDR.

Let me know if you have any other questions!

 

Thanks,

Tommy

[DoctorWkt]

Thanks for the suggestions, Tommy. I actually found a different path but now I'm stuck elsewhere. I found the MIG files for the DDR component in the resource center. I've been able to import these and create a component called mig_7series_0. I've also imported the ram2ddrxadc.vhd file, also from the resource center. I modified this file so that it uses the "mig_7series_0" component and not the "ddr" component (I didn't set the DDR name up when I generated it).

I have instantiated the ram2ddrxadc component in my top-level file, along with a port map. Ditto a 200MHz clock. Synthesis runs OK. However, when I run Implementation, I get these critical errors:

[Netlist 29-160] Cannot set property 'SLEW', because the property does not exist for objects of type 'pin'. ["/home/wkt/Vivado/Ram2DDR/
Ram2DDR.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/ mig_7series_0.xdc":33]

Looking at that xdc file, it looks like the pin mapping for the FPGA to the DDR chips. Can anybody explain why the xdc file is causing these errors? Line 33 and friends say:

# PadFunction: IO_L23P_T3_34
set_property SLEW FAST [get_ports {ddr2_dq[0]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr2_dq[0]}]
set_property IOSTANDARD SSTL18_II [get_ports {ddr2_dq[0]}]
set_property PACKAGE_PIN R7 [get_ports {ddr2_dq[0]}]

Now that I've seen Tommy's post, I'll also go and try that. I'll report back later!

What I'm aiming to do here is to make a simple VHDL project that uses the SRAM2DDR component, along with a list of instructions as to how I built it from scratch. This will serve as a useful how-to guide for others who don't know how to use the SRAM2DDR component.

Cheers & thanks for any feedback, Warren

[DoctorWkt]

I've just tried Tommy's suggestion. I imported the "Ram2Ddr_RefComp/Source/Ram2DdrXadc_Ref_Comp/ram2ddrxadc.vhd" file into a new project. I then imported (as IP) the file "ddr.xco". I added a 200MHz clock. In the top-level project file, I created components "clk_200M" and "ram2ddrxadc", and I added port maps for both of them.

But when I go to do Synthesis, I get exactly the same SLEW warning that I got when I used the MIG generator. This time the warning is for the same lines, but these are for a constraints file that was imported with the "ddr.xco" IP.

So now I'm stuck! What am I doing wrong? There must be a missing step that I'm not following.

James, if you read this, can you pass it up to the folk that wrote the SRAM2DDR component for comment?

Thanks all! Warren

[TommyK]

Hi Warren,

Are you constraining the DDR signals in your XDC? That might be what's causing your problems. The MIG constrains these pins for you.You still need to declare them as outputs from your top module though. Let me know if this works!

 

Thanks,

Tommy

[DoctorWkt]

Hi Tommy, sorry for the delay in writing, I've had other things that needed attention. Yes, I've tried putting the definitions of the pins in my top-level VHD file but I'm still getting the same warnings. I've looked at the looper demo and it seems to put the pin definitions in the top-level Verilog file (I don't know Verilog).

Is there a VHDL example around that uses the SRAM2DDR component that I could look at? Anybody?

Thanks all! Warren

[DoctorWkt]

Hi Warren,

I made a bare bones top module that includes the SRAM2DDR component. You should be able to work from here to do what you're trying to do.

 

Good luck!

Tommy

top.vhd

Wow, many thanks for that Tommy. I'll download it and have a look.

Cheers All, Warren