Weston Posted July 24, 2015 Share Posted July 24, 2015 I was curious if there was a published copy of constraints for the Nexys4-DDR that had constraints for the DDR2. The provided constraint file does not seem to have constraints for that defined nor do any of the sample projects. Thanks! Link to comment Share on other sites More sharing options...
Tomasz Hemperek Posted July 24, 2015 Share Posted July 24, 2015 At the bottom of page: https://digilentinc.com/Products/Detail.cfm?NavPath=2,400,1338&Prod=NEXYS4DDR Document: DSD-0000481 Link to comment Share on other sites More sharing options...
hamster Posted July 24, 2015 Share Posted July 24, 2015 The most likely reason would be that when you use the hardened memory controller all the pin locations are defined by the options chosen for the memory controller IP component - you get to select the bank, but not the location of the individual pins. Link to comment Share on other sites More sharing options...
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Weston
I was curious if there was a published copy of constraints for the Nexys4-DDR that had constraints for the DDR2. The provided constraint file does not seem to have constraints for that defined nor do any of the sample projects.
Thanks!
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