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Nexys4-DDR DDR2 Constraints


I was curious if there was a published copy of constraints for the Nexys4-DDR that had constraints for the DDR2. The provided constraint file does not seem to have constraints for that defined nor do any of the sample projects. 


Edited by Josh
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The most likely reason would be that when you use the hardened memory controller all the pin locations are defined by the options chosen for the memory controller IP component - you get to select the bank, but not the location of the individual pins.

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