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Modelling SRAM in VHDL


DoctorWkt

Question

Now that I've got one CPU working using block RAM, my next project is to design a CPU which uses the SRAM to DDR component on the Nexys4 DDR board. I'd like to do some behavioral and timing simulation of the SRAM first, using GHDL and Vivado.

Is there a VHDL model for this SRAM, or can somebody point me at a model which I could adapt? I did look on the Digilent VHDL components page https://www.digilentinc.com/classroom/VHDLcomponents/ but I didn't see it there. I have found several SRAM models, but none seem to deal with the timing delay or the upper/lower byte input.

Slightly off-topic (because it is not Digilent specific). I need to supply a 200MHz clock to the component. I'm guessing I use a Vivado clock wizard to make this.

Thanks in advance for any suggestions, pointers. Warren

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Hi Warren,

We have the VHDL model for the SRAM to DDR component available here on our wiki. It looks like it deals with the upper and lower bytes and has some timing stuff (at least according to the wiki page; I'm not super familiar with FPGAs so I can't guarantee I'm reading it correctly).

Let me know if you have any more questions.

Thanks,
JColvin

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Ah yes, but I want to simulate the SRAM in GHDL and/or Vivado so that I can see the waveforms and I can debug things before I take my design to hardware. I could modify an existing model such as this one: https://www.doulos.com/knowhow/vhdl_designers_guide/models/simple_ram_model/ , but I'm not sure how to model the timing delay. Can I just add a wait for tRC ns on a read operation, and wait for tWR ns on a write operation?

Thanks, Warren

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Have a look at http://people.sabanciuniv.edu/erkays/el310/MemoryModels.pdf it contains a example of how do do what you want. It's called 'transport' - it is how you can schedule something to happen after an event. Here's an example:

 

if (falling_edge(WE_b) and CS_b = ‘0’) then
  –- enter write mode
   data <= transport “ZZZZZZZZ” after t_WHZ;
end if;

 

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Could someone help me interpret the bus timing diagram on the SRAM2DDR wiki page? There are two timing parameters: tRC (read cycle time) = min 210 ns, and tWR (write cycle time) = min 260 ns.

The read timing diagram shows valid data immediately after ram_cen and ram_oen go active low, and lasting for tRC. Does this mean that the read data is available immediately? I was expecting that there would be some delay. And, does it mean that the address value has to be asserted for at least tRC? Actually, now I'm even more confused because the valid data in the diagram is on ram_dq_i which is an input to the component.

On the write timing diagram, ram_wen and ram_cen are enabled low and the address is kept valid for tWC. The ram_dq_i input data to the component isn't shown. The ram_dq_o output becomes valid at an indeterminate time after ram_wen.

Also, there's no output on the SRAM side to let the user know when the read data is available and when the write has been successful. So, how does the user know when reads and writes are successful?

I guess I'm still new to real hardware timing diagrams :-)

Thanks in advance for any help, pointers to useful web sites. Cheers, Warren

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