Now that I've got one CPU working using block RAM, my next project is to design a CPU which uses the SRAM to DDR component on the Nexys4 DDR board. I'd like to do some behavioral and timing simulation of the SRAM first, using GHDL and Vivado.
Is there a VHDL model for this SRAM, or can somebody point me at a model which I could adapt? I did look on the Digilent VHDL components page https://www.digilentinc.com/classroom/VHDLcomponents/ but I didn't see it there. I have found several SRAM models, but none seem to deal with the timing delay or the upper/lower byte input.
Slightly off-topic (because it is not Digilent specific). I need to supply a 200MHz clock to the component. I'm guessing I use a Vivado clock wizard to make this.
Thanks in advance for any suggestions, pointers. Warren
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DoctorWkt
Now that I've got one CPU working using block RAM, my next project is to design a CPU which uses the SRAM to DDR component on the Nexys4 DDR board. I'd like to do some behavioral and timing simulation of the SRAM first, using GHDL and Vivado.
Is there a VHDL model for this SRAM, or can somebody point me at a model which I could adapt? I did look on the Digilent VHDL components page https://www.digilentinc.com/classroom/VHDLcomponents/ but I didn't see it there. I have found several SRAM models, but none seem to deal with the timing delay or the upper/lower byte input.
Slightly off-topic (because it is not Digilent specific). I need to supply a 200MHz clock to the component. I'm guessing I use a Vivado clock wizard to make this.
Thanks in advance for any suggestions, pointers. Warren
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