Variable Valve Timing Proof of Concept

[CorradoSLC]

So, I'm going about this project where I am designing a system that would control the timing of intake and exhaust valves in internal combustion engines. I will have a signal generator give me pulses to act as the engine position sensor, and just LED's to act as valve actuator outputs. Later down the road, if I have time, I will add other features like a throttle potentiometer that could also affect timing possibly a driving mode selector, who knows. Anyway, I am having trouble figuring out how to have my board receive the signal from the signal generator. I'm thinking I could use the onboard ADC pins to detect a high or low input. It needs to be able to pick up the rising edge of each pulse from the signal generator to index a count which I am also trying to figure out. Overall, I don't think I'll have too much trouble if I can figure out how to receive the rising edge of the pulses.

The attached picture is a flow chart of how I plan on going about the logic. The pulse from the signal generator will index a 16 bit count that represent 16 points on a circle which will be used to determine engine position.

Abbreviations are as follows:

TDC = Top dead center bit

BDC = Bottom Dead Center bit

C = count of clock cycles between pulses

X = medium speed setpoint of clock counts

Y = High speed setpoint of clock counts

EO, EC, IO, IC = Exhaust and intake open and close setpoints of engine position

P = Engine position

I can make it as simple or complex as I want once I figure out the base design.

Any input would be much appreciated!

[CorradoSLC]

Anyone have any insight?

[Josh]

Hey, we we're talking about this and we think the FPGA forum would be best while your project is being created.

-Josh

[JColvin]

Hi CorradoSLC,

In terms of capturing your rising edges, I would check out this other forum post that we have here where a user is using the ADC to determine if an incoming signal is above or below a certain threshold.

Let me know if you have any more questions.

Thanks,
JColvin

[hamster]

Hi CorradoSLC,

I guess you are not getting much input as we are having trouble working out what your question is!

Depending on your design, have you thought of using using an optical rotary encoder? Unless you use a high resolution sensor  you will need to be predicting the future (i.e. you know how fast the crank was turning in the past, so you will have to assume that it is turning that fast in the future until you get another pulse from your sensor). 

As to conditioning the input signal, another option might be just a comparator on the input so it changes the state of a digital I/O pin on your controller.

But it is important to note that you can't reliably detect the highest or lowest points on a a signal this way as it will jitter back and forth with noise on the signal, or maybe fail to detact at all! But you can only reliably detect when it crosses a reference point somewhere near the middle level of the signal's range. Because of this it might mean that you need the sensor to be mounted at 90 degrees to what you would expect, perhaps giving a 0 to 1 transition could be TDC, and a 1-0 transition is BDC.

You might also need to do a little bit of tweaking of the value in software to remove any offset, making the time in the 0 state equal to the time in the 1 state - e.g. if the sensor spends 80 ticks in the '1' state, and 120 ticks in the '0' state, then you know your TDC and BDC transitions are off by a total of 20 ticks (e.g. one is early and one is late, but not sure which is which), You could then manually tweak then reference level of the comparator to get it closer to 100:100 split, and have software deal to the rest of the uncertainty.

[CorradoSLC]

For my purpose, calculating the engine speed between the first and second pulse is fine without worrying about the speed change during the rotation. An encoder would also be a good idea, but then I would need to drive it with a motor that I know the exact speed of, and I don't have either of those components on hand. I have a hand written picture of how the pulses are supposed to act as a portion of a circle, but I don't have a scanner handy. I need to detect the rising edge of each pulse to start and stop a counter and index the position of the circle it is on.

[CorradoSLC]

Anyone care to elaborate? The comparator seems to be the best way to go, but I have no idea how to code or address it in the ucf.

[hamster]

Have a look in the schematic in https://davidkessner.wordpress.com/2011/05/01/adc-in-an-fpga/

Rather than feeding the LVTTL driver from the point labelled 'DOUT' you could feed it from reference level (e.g. a one in three pulse will give you a reference level in the capacitor that is approximately 1/3rd of the LVTTL high level). By adjusting the duty cycle of this signal the reference level for the differential input could be dynamically adjusted....

So you will need to find a PMOD socket that has a differential pair (looking a the schematic and data sheets), and one other signal, then just modify the relevant lines from the generic UCF file.

So if B2 and A3 were a differential pair, and J3 was an output that could drive your reference level you could modify this from the standard UCF file:

NET "PIO<72>" LOC = "B2"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JA1
NET "PIO<73>" LOC = "A3"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JA2
NET "PIO<74>" LOC = "J3"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JA3

To be

NET "RAW_INPUT" LOC = "B2"  | DRIVE = 2 ; # Bank = 1, Signal name = JA1
NET "REFERENCE_INPUT" LOC = "A3"  | DRIVE = 2 ; # Bank = 1, Signal name = JA2
NET "REFERENCE_PWM" LOC = "J3"  | DRIVE = 2; # Bank = 1, Signal name = JA3
 

You would then connect a resistor and cap to pin JA3, and connect the middle of that to JA2, and then connect your analog sensor's output to JA1.

Your top level FPGA design would then use these three top-level signals.