My counter doesn' count please Help!

[Davelynch]

Hello everyone,

I have met an issue when I use a generic counter and associate it when other component : my counter doesn't count.

Firstly, I have designed three distinct function : a 2 bit counter, a multiplexer and one function allow to use 7 segment displays of Basys2.

Then, I have associated these function in order to obtain one block diagram.

The output of the counter are used to activate anode of 7 segment displays and they also used as input of 4 to 1 multiplexer.

Finally the 4 to 1 multiplexer ptovide input for a block wich allow to light one of four 7 segement displays.

When, I test only my 2 bit counter, it work correctly but when I associate this counter with other blocs diagramm, it doesn't count and stay to 0.

I have tried to figure out but I haven't saw what's wrong with my design.

This my vhdl code of my design :

 

-------------------------------------------------------------------------------
--
-- Title       : x7seg
-- Design      : Seven_Segment_Displays
-- Author      : Unknown
-- Company     : Unknown
--
-------------------------------------------------------------------------------
--
-- File        : C:\My_Designs\Example10\compile\x7seg.vhd
-- Generated   : Mon Jun 29 16:12:59 2015
-- From        : C:\My_Designs\Example10\src\x7seg.bde
-- By          : Bde2Vhdl ver. 2.6
--
-------------------------------------------------------------------------------
--
-- Description : 
--
-------------------------------------------------------------------------------
-- Design unit header --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_unsigned.all;


entity x7seg is
  port(
       clk : in STD_LOGIC;
       clr : in STD_LOGIC;
       x : in STD_LOGIC_VECTOR(15 downto 0);
       a_to_g : out STD_LOGIC_VECTOR(6 downto 0);
       an : out STD_LOGIC_VECTOR(3 downto 0)
  );
end x7seg;

architecture x7seg of x7seg is

---- Component declarations -----

component counter_2
  generic(
       N : INTEGER := 2
  );
  port (
       clk : in STD_LOGIC;
       clr : in STD_LOGIC;
       q : out STD_LOGIC_VECTOR(N-1 downto 0)
  );
end component;
component hex7seg_case_statement
  port (
       x : in STD_LOGIC_VECTOR(3 downto 0);
       a_to_g : out STD_LOGIC_VECTOR(6 downto 0)
  );
end component;
component mux44
  port (
       s : in STD_LOGIC_VECTOR(1 downto 0);
       x : in STD_LOGIC_VECTOR(15 downto 0);
       z : out STD_LOGIC_VECTOR(3 downto 0)
  );
end component;

---- Signal declarations used on the diagram ----

signal nq0 : STD_LOGIC;
signal nq1 : STD_LOGIC;
signal digit : STD_LOGIC_VECTOR (3 downto 0);
signal q : STD_LOGIC_VECTOR (1 downto 0);

begin

----  Component instantiations  ----

U1 : counter_2
  port map(
       clk => clr,
       clr => clk,
       q => q( 1 downto 0 )
  );
  
  nq1 <= not(q(1));

  nq0 <= not(q(0));

U2 : mux44
  port map(
       s(0) => q(0),
       s(1) => q(1),
       x => x,
       z => digit
  );

U3 : hex7seg_case_statement
  port map(
       a_to_g => a_to_g,
       x => digit
  );

an(3) <= nq0 or nq1;

an(2) <= q(0) or nq1;

an(0) <= q(0) or q(1);

an(1) <= nq0 or q(1);



end x7seg;

 

 

 

[hamster]

Maybe your design is switching digits too fast? 

Normally with a 100MHz clock, I use the top 2 bits of a 20-bit counter, which multiplexes the display at around 100Hz.