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Maximum resolution for HDMI input/output on Zybo and Nexys Video?


Tim Ansell

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Hello,

The older Atlys boards had a Spartan-6 FPGA which meant the highest progressive resolution supported by the HDMI input and output was 720p (which was always frustrating). I was wondering if that had changed with the newer Series 7 devices like the Zybo or Nexys Video boards? I noticed that hamster was able to get 1080i working. Are SERDES even able to do 1080p theoretically?

Thanks for your help!

Tim 'mithro' Ansell

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Hi hamster,

I'm told that they took advantage of the fact that Xilinx, like most companies, underrates their chips capability (to be on the safe side) and then the appropriate clock was just told to run over the specified speed to achieve the 1500 (or 1485) Mb/s and that they did not experience any signal integrity loss. 

I can try to find out more, but from what I can tell, it's not anything fancy beyond just "overclocking" the chip.

Thanks,
JColvin

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Hi,

After chatting with a more experienced person than I, neither datasheet for the 7-series chip on the ZYBO or Nexys Video give a clear answer for if they can transfer 1080p due to HDMI using a slightly different signaling convention than what the datasheet reports in (TMDS vs the reported LVDS) for a specific application (networking), among other other things.

However, like Mendeln, we have had no trouble ever transmitting 1080p from the ZYBO or Nexys Video at 60Hz. For receiving the 1080p the Nexys Video did fine, but there were some complications encountered when using the ZYBO due to receiving being inherently slower than transmitting. There were other reasons as well, but I personally didn't understand them.

Thanks,
JColvin

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Hi JColvin,

You must find out and tell us more.... I"ve always worked from table 15 in the DC/Switching characteristics on page 13 of http://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf 

Because of the heatsink I can't verify the speed grade on the Nexys Video, but the schematics have it as being a -1 part. For -1 speed grade that puts the OSERDES at 950 Mb/s, just a little over the 750Mb/s needed for 720p or 1080i. The industry standard for 1920x1080 @ 60Hz is 1,485 Mb/s per channel, which is over 50% higher than the data sheet, so I can't see how you manage it.

Can you get somebody to tell us the secret? :)

However, the Nexys Video does have Dual Lane DisplayPort that can move about 6.40Gb/sec, plenty for 1080p...

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Hi JColvin,

Any chance you could put us in contact with the person who actually managed to get this work? I'd love to see some example code showing it is possible.

I know hamster (with a huge amount of effort) was able to get a 1080p working on the Spartan 6 (http://hamsterworks.co.nz/mediawiki/index.php/Spartan_6_1080p) but it isn't actually within the HDMI specification. 

Thanks!

Tim 'mithro' Ansell

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The Atlys and the Nexys 4 Video have TMDS buffer ICs on their HDMI output (rated well above 1.5Gbit/s) so the FPGA only has to drive a few centimeters of Tracks.

I've run 1080p on my Atlys without Problems.

Maybe it doesn't work if the temperature is at the upper end.

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Murxwitz, do you have any examples you can share that demonstrate it? The example that hamster made requires very careful manual placement of components and even then doesn't meet the HDMI specifications.

What about 1080p *input* rather then output?

Thanks!

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I wrote a simple VGA-Output an fed the output into Hamsters TMDS-Encoder -> simple 2:1 mux and the the oserdes of the Spartan.

testet it with 1280x720 and dann simply changed the videotiming and PLL-outputs, simple overclocking of the serdes.

very similar to Hamsters version: http://hamsterworks.co.nz/mediawiki/index.php/DVI-D_Serdes

 

About HDMI-Input: I just startet to do it (about 50% finish).

ALSO: I don't think it meets HDMI specification because of PLL-jitter

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My design works! It receives the bits at 1.485 Gb/s, and then sends them out again.

http://hamsterworks.co.nz/mediawiki/index.php/Artix_7_1080p_passthrough

That leaves the dynamic sampling phase adjustment, symbol alignment and decoding as an an exercise for the reader :).

One thing that stumped me for a while was that I needed to explicitly use a BUFIO for the fast clock, not letting it default to a BUFG.

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I tested my implementation (still have some sync issues in the decoder, so the screen looks a bit weird) and it looks the same:

1280*1024@60Hz 1080Gbit/s

1280*1024@75Hz ~135Gbit/s

1920*1080@60Hz 1485Gbit/s

I'm deserializing and decoding the data to 24bit color + hsync,vsyn,data_en and then serialize it back, output from RAM works so the issues must be in the receiver (I suspect the bitslip-function). And im using the automatic phase adjustment inside the iserdes.

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