[email protected] - Article In The Wrong Topic, And A Few Suggestions.

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I was having a look at [email protected], and noticed that "Resistance and Ohm's Law" shows up in the Digital/FPGA topic, not under the Analog topic.


I like the "Design Challenges", I would love to see a few more of them!


A follow-on from the stopwatch could be a full digital clock (e.g. display hours and minutes).


Some advanced design challenges to explore doing things wrong would be interesting too - e.g.


Problems with switch bounce

Switch bounce as the mechanics within a switch or push-button make intermittent connection as the move from 'open' to 'closed'. Build a design that counts how many times a switch 'bounces'. You can either display it on the 7 segment display or even just a binary count on the LEDs.


Do some switches have more bounce than others? Would you expect the amount of bounce to change as the switch ages?


Make a design that counts how long a switch or button bounces for.


Now extend your design to include logic to "debounce" the switch, and prove that this now works correctly, with only a single transition being registered for each switch "open/close"


Problems with async resets


A reset signal should be synchronised with the local clock before being acted upon, otherwise different parts of a design can come out of reset during different clock cycles. This design challenge is different than most - you need to make a design that fails to reset correctly when a push-button is released, even though it is correctly coded.




Look at this code.


  if rising edge(clk) then    if reset = '1' then      toggle <= switches;    else       toggle <= not toggle.    end if;  end if;


If switches are set to all "0"s or all "1"s then "toggle" should never have anything but all 1s or all 0s - anything else is an error.


Important make sure you use external inputs to prevent the optimizer from collapsing your logic through constant propagation.


Can you make a reset that works reliably?


Problems with Metastability

When you have asynchronous signals it is possible for flip-flops to get stuck in an "undecided" state for a short duration causing system errors.


Are you able to make a design that successfully proves that this can occur, and provide a rough estimate of how often it occurs in your design


The Spartan 6 FPGA has a start-up clock that can be used in your design to provide a second independent clock signal.



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Thank you so much for your feedback, we really want Learn to be a resource for our customers and need suggestions like yours to help us improve it. 


mmigliacio -- is the Learn.DigilentInc moderator and I've tagged her in this post so she can grab your feedback and put it into queue. 


Thank you so much for sharing it with us. 



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The "Resistance and Ohm's Law" page (a background topic/related materials page) showing up in the FPGA section is due to it being linked within a project (https://learn.digilentinc.com/Documents/238) and it's meant as a sort of subject refresher . Earlier on in the the life of the Learn Site we only made the projects as visible tiles, with the background topics and design challenges hidden. However, we have now made it so that the background topics and design challenges associated with the projects will show up as well.  Unfortunately, this does create a bit of confusion with some background topics existing in there without any context - but our awesome web developer has found a solution to minimize the cluster: you can sort between displaying All, Projects, Topics, and Design Challenges next to the categories. 


These are fantastic ideas! If you are interested in submitting a design challenge of your own, I would be more than happy to set it up on our Learn Site (crediting you for the work, of course). A lot of the interns here create these projects/challenges themselves, and we're continuing to get more material edited and posted for the public - so hopefully you'll have more to go through in the future!


I really appreciate all of your feedback, thanks for posting this! And definitely let me know if you have any interest in content contribution. 



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