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Hi Everyone! 

I have a verilog/Vhdl design that reads the input from a digilent pmod analog to digital converter (AD1) and send the output to another digilent pmod (digital to analog converter, DA2 or DA3). I checked that design on three different FPGA (Spartan6 lx9, Spartan 3 Starter kit and Zedboard). The design works fine on the above FPGAs. Now I decided to upgrade my design to run on a ZYNQ 7020, but it doesn't work. If the synchronization frequency is set to 20 MHz for example, I cannot see the clock to the corresponding pmod of the zynq board. If I slow down the frequency, I can see the clock but its amplitude is Small (around 200 mV compare to the reference voltage of 3.3 V). Moreover, I don't know why, but the clock signal seems to have an offset greater than 1V. I want to know if somebody before me faced the same problem?  If yes how did you solve it? The second question I would like to ask is to know if Digilent Engineers checked their pmods on the Zynq 7020? If yes, could you please provide us with a template design as reference to check on our board? Thank you for any suggestions. 

Hervé

Edited by KaitlynFranz

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I went ahead and tried my suggestion and it worked. I used a razor blade to cut the pin on the transistor with the arrow, and the SCLK signal on the corresponding Pmod pin looks great now. This does mean that the LED is unconnected, but oh well. I'm not sure why Xilinx designed their board like this, but this fix works. I attached a pic of which pin I cut to make it work.

 

IMG_20150714_145344.jpg

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Hi Josh! Thank you.

I hope they will provide me a template design that I could use to check the correct behavior of Digilent Pmods (AD1/DA2/DA3) on the Zynq xc7z020 - clg484acx1433, or maybe provide me some interesting feedback that may help me to fix my problems. Please let me know as soon as possible so that I can continue to move forward in my project.

Thanks again and keep in touch.

Best,

Hervé

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Hello,

It sounds like you are having the exact same problem as the guy in this thread https://forum.digilentinc.com/topic/704-pmodad1-did-not-work-with-zc702/ I am trying to investigate this problem, but we don't have a ZC702 on hand at the moment. One thing I would like to point out is that the Zedboard also uses a ZYNQ 7020. Have you made sure the constraints are mapped out correctly?

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Hello tom21091!

Yes I know that the Zedboard also uses the Zynq 7020, I checked my code on the Zedboard and it works fine. The problem that I am facing is when I want to upgrade my design to run on a Zynq xc7z020 - clg484acx1433. I am running the same HDL code and the constraints are mapped out correctly. I use the following constraints in the UCF files:

## Clock pins
NET CLK_P LOC = D18 | IOSTANDARD = "LVDS_25";
NET CLK_N LOC = C19 | IOSTANDARD = "LVDS_25";

############################################################################
## Digilent PMOD1
############################################################################
NET "SCLK" LOC = "W5"  | IOSTANDARD = "LVCMOS25";
NET "CS" LOC = "E15" | IOSTANDARD = "LVCMOS25";
NET "DIN" LOC = "D15" | IOSTANDARD = "LVCMOS25";

############################################################################
## Digilent PMOD2 
############################################################################
NET "SCLK2" LOC = "P17" | IOSTANDARD = "LVCMOS25";
NET "SYNC" LOC = "V7" | IOSTANDARD = "LVCMOS25";
NET "DOUT" LOC = "W10" | IOSTANDARD = "LVCMOS25";

The "Zynq xc7z020 - clg484acx1433" uses a differential clock, that is why we have two clock pins (clk_p and clk_n). I added one instance of "IBUFGDS " in my top module, in such a way to use the differential clock:  IBUFGDS ibufgds_i (.I(CLK_P), .IB(CLK_N), .O(CLK) );

I also tried to play with different values of the driving strength by adding the "DRIVE" option (see below), but nothing change.

NET "SCLK2" LOC = "P17" | IOSTANDARD = "LVCMOS25" | DRIVE = 8;

It is really strange and I would like to fix this issue as soon as possible in such a way to move forward in the next step of my project.

Please let me know once you have some update. All suggestions are welcome!

Thanks.

Hervé

 

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Hi Hervé, 

I unfortunately do not have news for you, but I have contacted tom21091 to make sure that this forum thread did not accidentally fall off of his radar. 

Thank you for your patience,
JColvin

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Hi Herve,

Sorry for the delay! It's tough for me to figure out the problem, since it seems to be a problem setting up the Xilinx board you have. I think we have a ZC702 in the office, so I can test your project and see what I can find out if you post it!

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Hi Herve,

Sorry I've been pretty busy the last couple days, but I might have found something that could help. I came across this Xilinx forum post http://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/ZC702-pmod-problem/td-p/455926/page/2

It mentions that the Pmod pins are connected to FETs that drive the LEDs. I'm not exactly sure how you would fix this. I think this question would be best suited for Xilinx support, as it is their board and seems to be a problem on their side of things. I hope this helped!

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Hi Tom21091,

I already checked that forum before but it doesn't explain how to disconnect the Gates of the FETs connected to the LEDs (Assuming that this is related to the problem we are facing).

Did you try to run the design that I sent you on your ZC702 in the office? Did you get anything?

Thank you.

Herve

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Hi Herve,

I did try out the design, and I received similar results. I believe that this might be a physical limitation of the board, but again, it's not our board so don't take my advice to heart. After a bit more digging, I found out that the voltage level shifter in the ZC702 (TXS0108E) has a max possible data rate of 60Mbps. This is without all the extra capacitance from the other components on the board.

The other forum post mentions lifting the gate pins from the FETs connected to the LEDs. This would reduce capacitance and would improve your signal. This can be done by de-soldering the pins on the board or severing the physical connection in some way (wire cutters?). Once again, this is not our board, so take my advice with a grain of salt.

Best,

Tommy

Edited by tom21091

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Hi tom21091!

Thank you for your investigations. I really appreciate your help :)

I believe that the parallel connection between the LED and the Pmods pins on the ZC702 is at the origin of the physical limitations.

However, I cannot cut the pin on the transistor otherwise I will lose the guarantee and won't be able to exchange that board anymore.

Thanks again and keep in touch!

 

Regards,

Herve

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Hi Bahare,

If you just want to view or edit these files you can open them with any text editor like notepad or notepad++. If you want to use these files in a design then you will need Xilinx ISE to open them. You can either add them to a new project or an existing project.

Either way once you have the project open you can right click on the chip name and select "add sources" to add the files. 

ISEss.thumb.jpg.1d3d3281baa5dc265c09261e

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