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warning during counter implementation

Go to solution Solved by hamster,

Question

Hi everyone !

I need some help please : when I try to implement a counter in active HDL I have this warning message :

" Route:455 - CLK Net:U1/q<23> may have excessive skew because
2 CLK pins and 1 NON_CLK pins failed to route using a CLK template "

I explain :

Firstly I have designed a basic counter with Basys2 board :

```library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;

entity counter_2 is
generic (N : integer := 4);
port(
clr : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(N-1 downto 0)
);
end counter_2;

--}} End of automatically maintained section

architecture counter_2 of counter_2 is
signal count: STD_LOGIC_VECTOR(N-1 downto 0);
begin
process(clk, clr)
begin
if clr = '1' then
count <= (others => '0');
elsif clk'event and clk = '1' then
count <= count + 1;
end if;
end process;

q <= count;

end counter_2;```

Then I have produced 24-bit (q(23) downto q(0)) clock divider, my goal is to divide original frequency and obtain 2.98 Hz in using q(23) as output of the clock divider :

```library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;

entity clkdiv2 is
port(
clk : in STD_LOGIC;
clr : in STD_LOGIC;
clk3 : out STD_LOGIC

);
end clkdiv2;

--}} End of automatically maintained section

architecture clkdiv2 of clkdiv2 is
signal q: std_logic_vector(23 downto 0);
begin
process(clk, clr)
begin
if clr = '1' then
q <= X"000000";
elsif clk 'event and clk = '1' then
q <= q + 1;
end if;
end process;

clk3 <= q(23);
--clk48 <= q(19);
--clk190 <= q(17);

-- enter your statements here --

end clkdiv2;```

Finally I have used block diagram of the first counter and the clock divider to light the eight LEDs of Basys 2 as binary counter :

```-------------------------------------------------------------------------------
--
-- Title       : count8_top
-- Design      : Counter
-- Author      : Unknown
-- Company     : Unknown
--
-------------------------------------------------------------------------------
--
-- File        : c:\My_Designs\Example8\compile\count8_top.vhd
-- Generated   : Mon Jun 15 22:01:20 2015
-- From        : c:\My_Designs\Example8\src\count8_top.bde
-- By          : Bde2Vhdl ver. 2.6
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_unsigned.all;

entity count8_top is
port(
clk : in STD_LOGIC;
btn : in STD_LOGIC_VECTOR(3 to 3);
ld : out STD_LOGIC_VECTOR(7 downto 0)
);
end count8_top;

architecture count8_top of count8_top is

---- Component declarations -----

component clkdiv2
port (
clk : in STD_LOGIC;
clr : in STD_LOGIC;
clk3 : out STD_LOGIC
);
end component;
component counter_2
generic(
N : INTEGER := 8
);
port (
clk : in STD_LOGIC;
clr : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(N-1 downto 0)
);
end component;

---- Signal declarations used on the diagram ----

signal clk3 : STD_LOGIC;

begin

----  Component instantiations  ----

U1 : clkdiv2
port map(
clk => clk,
clk3 => clk3,
clr => btn(3)
);

U2 : counter_2
port map(
clk => clk3,
clr => btn(3),
q => ld( 7 downto 0 )
);

end count8_top;```

Finally when I implement the block diagram corresponding to the code above, I have this warning :

" Route:455 - CLK Net:U1/q<23> may have excessive skew because
2 CLK pins and 1 NON_CLK pins failed to route using a CLK template "

I don't understand what does it mean.

Edited by KaitlynFranz

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• Solution

Finally when I implement the block diagram corresponding to the code above, I have this warning :

" Route:455 - CLK Net:U1/q<23> may have excessive skew because
2 CLK pins and 1 NON_CLK pins failed to route using a CLK template "

I don't understand what does it mean.

Hi!​

Inside the FPGA there are clocking distribution resources (where the signals are able to to a wide area of the FPGA, with very low difference in the time that the clock edges get to their destinations), and then there are "the other stuff" that connects the individual bits of logic together.

The global clocks are a limited resource - it is really expensive in power and chip real estate to .get a signal to all parts of the chip at the same time, and because of this the tools will only really use them when it is required (e.g. when you have 100s of flip-flops driven by the same clock).

The warning is telling you "Hey! You only have a handful of flip-flops driven by this clock, so I've decided to use the low power, low performance signal routes - so your design won't have all the performance you might expect".  It is an attempt to tell you that it has given you what you asked for, not what is optimal for the underlying FPGA architecture.

The optimal solution is to use a "clock enable" signal

```	process(clk, clr)
begin
if clr = '1' then
q <= X"000000";
elsif rising_edge(clk) then
if clock_enable = '1' then
q <= q + 1;
end if;
end if;
end process;```

And then have the clock_enable set for one cycle when the clock dividing counter rolls over to 0.

That way both counters can be clocked by the same clock signal, and that clock signal will use the clocking networks.

PS. Using async 'clr' is usually a bit dicey, and may not work reliably depending on the timing of when the signal is removed. Unless you are careful different parts of a design can come out of reset on different cycles, due to delays in the FPGA..

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Hello hamster.

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