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memol63

pmodAD1 did not work with ZC702

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hi,

I am using PMOD AD1 and PMOD DA2 on ZC702 Eval Board but it dose not work. Befor that I used my code with spart 3a, spartan6 and zedboard and my code work for all of them but when I used that code for the zc702 it dose not work. I use clock division to send 20 Mhz : 

This is my code: 

library ieee;
use ieee.std_logic_1164.ALL;
--use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.all;

 

Library UNISIM;
use UNISIM.vcomponents.all;


entity ad1_da2 is
    port(   
                SCLK_P : in std_logic;
                SCLK_n : in std_logic; 
 CS : out std_logic; -- chip select for ADC(active low)
            SYNC : out std_logic; -- SYNC for DAC
            DIN : in std_logic; -- ADC
            DOUT : out std_logic; -- DAC
 
            SCLK : out std_logic; -- ADC
            SCLK2: out std_logic -- DAC
            );
end ad1_da2;
 
architecture Behavioral of ad1_da2 is    


            component IBUFGDS is
    port (
      I : in std_logic;
      IB : in std_logic;
      O : out std_logic
    );
     end component;
    -- FSM states
    type state_type is (IDLE, READ_DATA, FUNC, WRITE_DATA);
    -- initial state
    signal state : state_type := READ_DATA;
    -- data from the ADC
    signal data : std_logic_vector(11 downto 0);
    -- counter variable
    signal cnt : integer range 0 to 20 := 0;
    -- counter for clock division
    signal clkdiv : integer range 0 to 10;
    -- new clock from division
    signal newclk : std_logic := '0';
    signal risingedge : std_logic := '1';
    -- reset signal
    signal reset : std_logic := '0';
 

    signal clk : std_logic;
    

   
begin

 

    SCLK <= newclk;
    SCLK2 <= newclk;


        begin
            if (reset = '1') then
            elsif (rising_edge(CLK)) then
                if (clkdiv = 10) then -- divide 200MHz by 10
                    risingedge <= risingedge xor '1';
                    newclk <= newclk xor '1';
                    clkdiv <= 0;
                else
                    clkdiv <= clkdiv + 1;
                end if;
            end if;
        end process clock_divide;


    main : process (CLK, reset)
        begin
            if (reset = '1') then
            elsif (rising_edge(CLK)) then
                if (clkdiv = 10 and risingedge = '1') then
                case state is
                  when IDLE =>
                    CS <= '1';
                    SYNC <= '1';
                    if (cnt = 16) then
                        cnt <= 0;
                        state <= READ_DATA;
                    else
                        cnt <= cnt + 1;
                        state <= IDLE;
                    end if;
                when READ_DATA =>
                    CS <= '0';
                    SYNC <= '1';
                    cnt <= cnt + 1;
                    if (cnt<4) then
                        cnt <= cnt + 1;
                        state <= READ_DATA;
                    elsif (cnt > 3 and cnt < 16) then
                        cnt <= cnt + 1;
                        -- the first 4 bits are 0000 only read the last 12
                        data(15-cnt) <= DIN;
                        state <= READ_DATA;
                    elsif (cnt = 16) then
                        cnt <= 0;
                        state <= FUNC;
                    end if;
                -- signal processing would go in this state
                -- but for now we don't do anything in here
                when FUNC =>
                    CS <= '1';
                    SYNC <= '1';
                    cnt <= 0;
                    
                       state <= WRITE_DATA;
                when WRITE_DATA =>
                    CS <= '1';
                    SYNC <= '0';
                    if (cnt = 0 or cnt = 1) then
                        cnt <= cnt + 1;
                        DOUT <= '0';
                        state <= WRITE_DATA;
                    elsif (cnt = 2 or cnt = 3) then
                        cnt <= cnt + 1;
                        DOUT <= '0';
                        state <= WRITE_DATA;
                    elsif (cnt > 3 and cnt < 16) then
                        cnt <= cnt + 1;
                        DOUT <= data(15 - cnt);
                        state <= WRITE_DATA;
                    elsif (cnt = 16) then
                        cnt <= 0;
                        state <= IDLE;
                    end if;
                end case;
            end if;
        end if;
    end process main;

          
                 ibufgds_0 : IBUFGDS
                     port map (
                        I => SCLK_P,
                        IB => SCLK_n,
                        O => CLK
                     );
end Behavioral;

 

 

Do you have an idea?

Edited by KaitlynFranz

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6 answers to this question

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Hi there,

I can try to help out, but unfortunately I don't have a ZC702 board anywhere to test your code myself. Have you gotten any error messages or warnings when you synthesize/implement this design? Also have you made sure the XDC is configured correctly? The code seems sound, especially since it worked on the other devices.

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On this link here : https://www.dropbox.com/s/pd83chcqczeimph/Data Acquisition System - Demo Project.zip?dl=0

you can find a data acquisition project for Pmods AD1 and DA2. 
Please note that this project is not released, so take it as it is.

There you can find implementation for both Nexys3 and Nexys2 boards, and both VHDL and Verilog languages. On the sources folder you will find a good component for PmodAD1.

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Cristian.Fatu 

I used this code but this code it is  not work on ZC702 also I checked this code on spartan3 and zedboard and spartan6 and I did not have a problem with these boards. These pmods work with the other board very well but there are not compatible with zc702.

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Sorry 

i am unskilled   i have one file for two pmod max5216(DAC) and max11205(ADC) but in this file just one pmod work and i want that ADC andDAC work togheter 

have you file ready C in SDK or one file that DAC and ADC work togheter?

 

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