NetFPGA-1G-CML reference manual (v4) has incorrect info on PCIe pinout (constraints)

[Bogdan Sorlea]

Hey,

In V4 version of the doc (and board?), http://digilentinc.com/Data/Products/NETFPGA-1G-CML/NetFPGA-1G-CML_rm_V4.pdf (currently linked on Digilent website), the pin constraints for pcie-rx3_p, pcie-tx3_p, pcie-rx3_n and pcie-tx3_n are wrong, as they are the same as pcie rx/tx port 2 (see first half of page 19 of aforementioned pdf).

In V3, https://www.digilentinc.com/Data/Products/NETFPGA-1G-CML/NetFPGA-1G-CML_rm_V3.pdf (found via Google), I discovered what might be the correct values - it would be nice if someone could confirm them as being right (page 19).

[NAEastland]

Hey Bogdan,

Thank you for pointing out this discrepancy. We will be verifying the pin constraints and updating the reference material to reflect the correct constraints.

Regards

[JColvin]

The pins listed in version 3 (pcie-rx3_p = P2,  pcie-tx3_p = R4,  pcie-rx3_n = P1,  pcie-tx3_n = R3) are correct. I'll submit a change request for that particular reference manual.