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vicvicvar

basys3
Creating a 25 Mhz clock on the Basys 3

Question

Hello Forum ,

Its my first Post so I hope it helps everyone ;)

I have this code for generating a 25 Mhz clock having a 50 Mhz clock as main using the basys3 board. I use the LSB as the clock because it will goes 1/2 of the main clock of 50Mhz

*//////////////////////* START OF CODE

//Clock
module clkdiv(
input wire mclk ,
input wire clr ,
output wire clk25
);

reg [24:0] q;

always @(posedge mclk or posedge clr)
    begin
        if(clr == 1)
            q <= 0;
        else 
            q <= q+1;
    end

assign clk25 = q[0];

endmodule

*////////////////////////* END OF CODE 

So whenever I want to call it I just make a instance of this class. 

In Vivado, when I open my synthesized project and click [Tools ---> Edit devices properties] This is where I select my clock frequency as 50 MHZ { Please see image attached }

So my questions are :

  1. Is this the proper way to set up a clock using Vivado and the Basys3 Board?
  2. In the main page of the Basys3 it says that one can get a clock as high as 450 Mhz but in the options of the [Tools ---> Edit devices properties]  I can only find clocks as high as 66 Mhz

And just some basic ones 

  1. Why Vivado takes sooo long to synthesized, implement and generate the bitstream of an easy and small code? Just implementing in hardware an AND gate takes me 5 minnutes to download the program to the board. Is there a quicker way ?

 

Thanks Forum .

 

 

50 Capture.PNG

Edited by KaitlynFranz

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12 answers to this question

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Hi Vicvicvar,

Are you you sure that your clock is 50MHz? The Basys3 board has only one oscillator on it, and it is 100 MHz.

That window where you set the configuration clock rate sets how quickly the FPGA attempts to read from it's configuration Flash, not how quick the external clock is.

If you want to know everything about the clocking resources on your FPGA, have a look at this user:

guide: http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

Chapter 3 has all the details on how to make faster/slower clocks.

 

JColvin and vicvicvar like this

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Hi, you can refer to this post about the clock generation. Although it is for Basys2, it should be good for Basys 3

 

 

Edited by JColvin
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Hi,

You may also find this post helpful on creating a 400 MHz clock out of a 100 MHz clock.

As for Vivado synthesizing taking awhile, that is (unfortunately) just going to be the case for programming any FPGA. Hamster explains the reasons here.

Thanks,
JColvin

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Thanks everyone for helping me with the clock. Your links are very helpful !

BTW Im trying to drive a VGA controller. Will you know of an example with the basys 3 board? 

Thanks

 

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Hi, we don't have any for Basys 3 but in the book Digital Design using VHDL / Verilog. There is an example using VGA with Basys 2. The flow and design is the same. 

In addition, you can google the VGA FPGA. There should be bunch of examples. 

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Hello,

You can find a vhdl and XDC file in attachment which implements 1280 x 1024 @ 60Hz. To run the example you should add a clocking wizard IP in your design with "clk_wiz_0" name at 108 MHz.

In this example, the VGA bits are connected to sw(11:0).

If you want to change the resolution, you can find the VGA timing on the following link: http://tinyvga.com/vga-timing . For this, you should change the constants from the VGA.vhd and the clock frequency.

Regards,

Cristian

VGA.vhd

basys3.xdc

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I tried the VGA.VHD file, along with the constraint file attached above but the simulation does not compile. Any thoughts? I added the clocking wizard as well.  The constraint for sw[8] appears to be correct

 

[DRC 23-20] Rule violation (BIVB-1) Bank IO standard Support - Bank 34 has incompatible IO(s) because: The LVCMOS33 I/O standard is not supported.  Move the following ports or change their properties:  
clk
 

[DRC 23-20] Rule violation (BIVB-1) Bank IO standard Support - Bank 34 has incompatible IO(s) because: The LVCMOS33 I/O standard is not supported.  Move the following ports or change their properties:  
sw[8]
 

[Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
 

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Hi jasonmain,

I just ran with no issue the VGA.vhd including the basys3.xdc. I added the clocking wizard with an 108 Mhz output as instructed. Could you attach a screen shot of you project settings like i did below as well as attach the xdc file you are using in the project.

cheers,

Jon

basys3_vga_esc.jpg

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5 hours ago, jpeyron said:

Hi jasonmain,

I just ran with no issue the VGA.vhd including the basys3.xdc. I added the clocking wizard with an 108 Mhz output as instructed. Could you attach a screen shot of you project settings like i did below as well as attach the xdc file you are using in the project.

cheers,

Jon

basys3_vga_esc.jpg

 

 

Hello Jpeyron!

Thanks for the quick response. After a long night of trying to get this to work, I took another look at it from scratch and got it running.  I really appreciate your help and quick response.  I am guessing that the clock wizard being set for 108MHz corresponds to the pixel (frequency) clock of the resolution chosen, correct?

http://tinyvga.com/vga-timing/1280x1024@60Hz

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Hey jasonmain,

I wanted to give this code a try for my vga project. I have been able to generate the bitstream and program my board, however, if I connect it to my screen, the screen doesn't show anything. It stays in the self test mode. I would appreciate if you could help me with the same

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Hi @Vinit Shukla

What sort of screen resolution does your display support? I presmed you changed the constants in the provided in the  VGA.vhd file as per the settings listed for your particular display on this page?

Thanks,
JColvin

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