Genesys DDR with ISE 14.7

[zygot 221]

I need to use the Genesys DDR2 SODIMM connected to logic ( no soft processor ) using the ISE flow instead of XPS. Has anyone at Digilent  a working project similar to the DDR test available for the Atlys board? Curiously, the MIG tool doe not let me assign the correct pin to the ddr_wen signal.

Edited May 28, 2015 by KaitlynFranz
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[sLowe 24]

Hey Zygot,

I also ran into this problem. It seems like the updated MIG doesnt like that the DDR_wen pin is located on a vref pin although no data pins are on the same bank. There is a workaround that can be found here. https://reference.digilentinc.com/genesys:mig  It includes how to set up the MIG and PLL to DCM wizards and how to manage the .prj files to correct the ddr_wen signal. Also at the end is a working Genesys project running the ISE generated test project.

This solution was inspired by This thread. In short you select an available pin for the wen signal then after the fact go change the MIG .prj file to attach the correct pin.

Let me know if you need some more clarification!

- Sam