to communicate fpga board to pc via ethernet

[kashyap0]

hi
i am trying to cummunicate to pc with fpga board. i am using atlys board of digilent company in which spartan-6 (xc6slx45csg324c) is connected to marevell 88E1111 phy chip.

my frame is:-

constant udp_frameA :frame60:=
      (x"FF",x"FF",x"FF",x"FF", -- mac dest
        x"FF",x"FF",x"00",x"00",
        x"00",x"04",x"14",x"13", -- mac src
        x"08",x"00",x"45",x"00", -- IP header
        x"00",x"2E",x"00",x"00",
        x"00",x"00",x"40",x"11",
        x"7A",x"C0",x"00",x"00", -- IP src
        x"00",x"00",x"FF",x"FF", -- IP dest
        x"FF",x"FF",x"00",x"00", -- port src
        x"50",x"DA",x"00",x"12", -- port dest + len
        x"00",x"00",x"41",x"41", -- checksum udp + data "A"
        x"41",x"41",x"41",x"41",
        x"41",x"41",x"41",x"41",
        x"41",x"41",x"41",x"41",
        x"41",x"41",x"41",x"41");    
and i am getting same frame on simulation and chipScope but i am not getting this frame in proper order on Wireshark. Wireshark result attached with it.

please find this attachment.
please respond me as soon as possible.

[Cristian.Fatu]

This issue was answered here: https://forum.digilentinc.com/topic/551-to-communicate-atlys-fpga-board-to-pc-via-ethernet/ by user Albi.

Regards,

Cristian