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JColvin

Sending messages on the PmodCLP

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That would depend on how you connect the board and PMOD. The PmodCLP has a 12-pin PMOD connector and one 6-pin PMOD connector - but the Basys2 has four 6-pin connectors.

Depending on how you intend to physically connect the two together the signal to pin definitions in the UCF file will be different.

If you could tell us the top level signals in your design and how you have connected the boards then it should be pretty easy to work out the required UCF file entries you will need.

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Hi,

Have you checked out the support documents at the bottom of it's product page? There are several demonstration projects for the PmodCLP written in a variety of languages including C, C++, Verilog, and VHDL available for download.

Let me know if you have any more questions.

Thanks,
JColvin

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There is 24 different ways that you can plug the PmodCLP into a Basys2 board.

Unless you can tell us how you have connected it has enough information to provide you with any help - maybe add a photo to your post?

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Yes, that kit can work effectively for connecting the Pmod to the Basys 2. The split 12-pin cable can have its two 6-pin ends connect to two of the Basys 2 6-pin headers and the second 12-pin cable will be able to make the final needed connection for the remaining 6 pins on the PmodCLP. 

Note that for the split cable that the "B" side of the split is the side oriented to the "marked" 12-pin end of the cable. I'm not sure how this was supposed to make sense when that cable was selected for the kit, but at least it is an easy adjustment.

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Hi there,

There isn't currently a demo for the PmodCLP targeting the Basys2 but if you look on the product page there are several that target the Nexys 3. If you download the demo in either VHDL or Verilog you can go into the sources file and look at the .v file. From there you can modify the UCF file to target the Basys2. 

Kaitlyn

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This is for the Nexis UCF 3

##JA
#Net "JA<0>" LOC = T12 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L19P, Sch name = JA1
#Net "JA<1>" LOC = V12 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L19N, Sch name = JA2  
#Net "JA<2>" LOC = N10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L20P, Sch name = JA3
#Net "JA<3>" LOC = P11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L20N, Sch name = JA4
#Net "JA<4>" LOC = M10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L22P, Sch name = JA7
#Net "JA<5>" LOC = N9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L22N, Sch name = JA8
#Net "JA<6>" LOC = U11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L23P, Sch name = JA9
#Net "JA<7>" LOC = V11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L23N, Sch name = JA10
  

   as it should be for the BASYS 2?

ucf.jpg

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Ricardo,

In the Nexys 3 Master UCF file you need to un-comment the pins that are used in the demo. So if you are trying to use the Pmod connector labeled as JA, pins 0 through 7, you need to un-comment those lines. Then you need to make sure they are named (the part in the quotation marks) the same as in the PmodCLP.vhd file when you declare them as inputs and outputs. 

I haven't finished the guide yet but as I said I will post it when it is done. 

Hope this helps in the mean time.

Kaitlyn

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Hi Ricardo,

I'm not sure what the timeline for the guide Kaitlyn mention is. I know that a number of the Forum Moderators, including myself, were gone at NI Week this past week so we were unable to devote a lot of time to the Forum.

FPGAs are not my strong suit so I am not able to help you out directly, but we'll definitely let you know when the guide is completed so that way anybody who as a question on changing UCF files will be able to have their question answered.

Thank you for your patience.

Thanks,
JColvin

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