JTAG-HS3 vs JTAG-HS2 when using Zynq with Vivado

[whasssaaahhh]

Hello,

I currently use a JTAG-HS2 cable with my Zynq development board. What would be the advantage or disadvantage of switching to a JTAG-HS3 cable with (exclusive) regard to using it with Zynq devices (Through Vivado 2014.4 and SDK)?

I found this comparison table :

http://www.digilentinc.com/choosing.cfm

I think the big difference towards Zynq is the PS_SRST support, however it's not clear to me what exactly this is? I can use the Zynq now with my HS-2 cable, put breakpoints, ... so I wonder what this extra feature might bring to the table.

I guess the 'no support for 2-wire JTAG' and SPI' is not an issue with Zynq devices (?)

best regards

 

[Josh]

I looked through the reference manuals for the two cables and I think I found what you're looking for. 

In the Xilinx Zynq-7000 and SoC Support section of the JTAG-HS3 cables it says:

The Xilinx Tools occasionally require the processor core of the Zynq-7000 to be reset during debug operations. The Zynq platform processor has a pin dedicated for this purpose (PS_SRST_B). Driving the PS_SRST_B pin low causes the processor to reset while maintaining any existing break points and watch points. The JTAG-HS3 is capable of driving this pin low under the instruction of Xilinx’s SDK during debugging operations. In order for this to work, pin 14 of Xilinx JTAG header on the target board must be connected to the PS_SRST_B pin of the Zynq (see Figs. 3 & 4). 

[Figs. 3 & 4]

The JTAG-HS3 uses an open drain buffer to drive pin 14 of the Xilinx JTAG header (see Fig. 5). This allows the HS3 to drive the PS_SRST_B pin when VCC_MIO1 is referenced to a different voltage than VCCO_0 (see Fig. 6). 

 Here's a link to the  relevant section in the JTAG-HS3 reference manual.

I hope this helps!

-Josh