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digicloud14

Help With A Zybo Video Design

Question

Hi all,

I have a Zybo Zynq-7000 Development board, and I'm attempting to create a design that uses the bidirectional HDMI port as an input. I want to take the HDMI input (with a desktop or laptop as the source) and write the video stream to memory, and then access the data in a Linux environment (I am using Xilinux, a graphical, Ubuntu 12.04 LTS-based Linux distribution for the Zynq-7000) to eventually send out the data over the internet. I'm having a bit of difficulty understanding how to correctly implement the design in Vivado (2014.4) which is why I'm here. I'm trying to use as many standard Xilinx or Digilent IP cores as possible to make the design straightforward since I am new to FPGA and Vivado. After wading through tons of documentation, I feel like I have a decent understanding of the general design flow for a video design, but as I said I do not have much experience here so I am looking for someone to hopefully point out my mistakes or point me in the right direction.

My current design uses a DVI2RGB IP core provided by Digilent (found here: https://github.com/DigilentInc/vivado-library/tree/master/ip/dvi2rgb_v1_4) which is then interfaced with the Xilinx Video In To AXI4-Stream IP Core (documentation found here: http://www.xilinx.com/support/documentation/ip_documentation/v_vid_in_axi4s/v3_0/pg043_v_vid_in_axi4s.pdf), which then goes to the Xilinx AXI Video Direct Memory Access (VDMA) IP core (documentation found here: http://www.xilinx.com/support/documentation/ip_documentation/axi_vdma/v6_2/pg020_axi_vdma.pdf). Finally, the output of the VDMA is interfaced with an AXI Memory Interconnect to connect it all to the processing system. I do not want to output the video stream that is being written to memory to a display output such as VGA, simply access the video data in Linux and send it out over the internet.

A few questions:

1. First and foremost, does my thought process for the design outlined above make any sense?
2. Do I need to use the Video Timing Controller and subsequently the Video Timing Controller IP cores for a design such as this? My assumption here is NO since the input is providing the clock (which in Vivado is being provided to the Video In To AXI4 and VDMA cores), and nothing is being outputted.

3. The DVI2RGB IP Core takes in TMDS as its input. Do I simply create ports labeled TMDS_Clk_p etc and connect to the input of the IP core? How does Vivado know (and subsequently, how does the board know) those ports I created are supposed to be for the HDMI input port?

4. Assuming my design works and I can successfully write the inputted video stream into memory using the VDMA, is the Xilinx Linux VDMA Driver (found here: http://www.wiki.xilinx.com/DMA+Drivers+-+Soft+IPs) my best bet for accessing the data in the VDMA in Linux? Or is Video4Linux2 (V4L2) something that I should be using here? I've read that V4L2 has compatibility with VLC which seems like a convenient way to then stream the video data over the internet.

Additionally, I was able to import an EDK HDMI_RX IP core into Vivado that is used in a Digilent GoPro Video Filtering Project (found here: https://github.com/LariSan/Digilent-Maker/tree/master/Zybo/zybo_video_demo)Should I be attempting to use this core instead of the DVI2RGB core? I chose the DVI2RGB because it was designed for Vivado rather than EDK, so I assumed it would be easier to use. I would eventually like my design to incorporate audio as well though, which I know DVI doesn't do.

Comments, criticism, advice, help; whatever you've got, it is very welcome here! Anything to steer me in the right direction. Sorry for the long post guys, I've always been a bit verbose :P I'll attach a screenshot of my Vivado block design to hopefully illustrate some of the things I mentioned about my design. http://i.imgur.com/rdXtuOf.png

Thank you,
Chris
 

Edited by KaitlynFranz
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Run,

I've tried every combination of removing the DDC port from the DVI2RGB core and commenting out the ports on the xdc, but I can't seem to get past the error.

 

Jieming, in part 3 of your first post, you mentioned that Vivado no longer handles inout as a single port. I think this is the problem I'm running into currently. You said I need to make changes to the top level module? Something like: 

HDMI_SDA <= HDMI_SDA_O when HDMI_SDA_T = '0' else 'Z';
    HDMI_SDA_I <= HDMI_SDA;

Could you elaborate on this part? I noticed those names match those in the Zybo Master XDC for the HDMI SDA and SCL. Is that what you meant by the top level module? Additionally, if there's anything from your project you could share that you think may help, I would greatly appreciate that!

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Hey Marshall and Jieming,

Thank you both for taking the time to help me out. After a few modifications to the XDC and design wrapper, I was able to get the DDC connections properly set up and successfully generated the bitstream for the design. I did get a critical warning stating that my design did not meet timing constraints, so I'm working on correcting those now using the information you posted above. You guys are extremely helpful, it is very much appreciated.

**Question about timing (sorry!)

Just to verify a few things: The Zybo has a max buffer bit clock of 600 MHz, so the recommended TMDS_Clk is 600/5 = 120 MHz. The DVI2RGB core requires a 200 MHz ref clock. In my design I am using the Processing System (PS), so similar to Run's design, I have an FCLK from the PS going into a clocking wizard.

Following Marshall's post, I commented out the timing constraints in the dvi2rgb xdc. When configuring my clocking wizard, do I also need to change mine from MCMM to PLL, even though I am using the Processing System? I'm not sure because Marshall's design does not use the processing system, he instead creates his own clock.

Finally, to constrain the TMDS_Clk to 120 MHz, is this simply done when I connect the inputs to the DVI2RGB core and specify that the signal is a clock and enter 120 MHz, as shown in this image? http://i.imgur.com/SINVpSG.png Or do I need to additionally add something to the Master_Zybo or DVI2RGB XDC? I'm just a bit confused here because Jieming mentioned to add this to my XDC:
create_clock -name sysclk -period 25 -waveform {0 12.5} [get_ports HDMI_CLK_P]

But that gives a frequency of F = 1/25 nanoseconds= 40 MHz, unless I am missing something.

I think my problem lies here. When attempting to generate a bitstream, it does so successfully without any errors, but I am still failing a timing constraint (much better then previously when I was failing several). Here is a view of my timing report http://i.imgur.com/WWZS1iu.png. As you can see, my CLK_OUT_5x_HDMI_clk timing fails with an actual pulse width of 1.212 nanoseconds. That gives a frequency of about 825 MHz, or 165 MHz x 5. So somewhere in the design there is a constraint keeping the TMDS clock at 165 MHz, even though I commented out the timing constraints in the dvi2rgb.xdc. When creating the ports for TMDS_Clk_p and TMDS_Clk_n I set them as 120 MHz clock signals as shown in the first image. But apparently this isn't holding? I'm thinking I need a line in the master xdc such as:

create_clock -name sysclk -period 8.33 -waveform {0 12.5} [get_ports HDMI_CLK_P]

So sorry for all the questions, but you have no idea how much you guys have helped me out.


Thanks,
Chris

Edited by digicloud14

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Run,

Thank you, that makes a lot of sense. I'll also switch to the PLL for the clocking wizard.

Marshall,

If you find yourself with time to spare and wouldn't mind doing the design with the PS, I certainly won't say no to that. Thank you!

Thanks,
Chris

Edited by digicloud14

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