Help With A Zybo Video Design

[digicloud14]

Hi all,

I have a Zybo Zynq-7000 Development board, and I'm attempting to create a design that uses the bidirectional HDMI port as an input. I want to take the HDMI input (with a desktop or laptop as the source) and write the video stream to memory, and then access the data in a Linux environment (I am using Xilinux, a graphical, Ubuntu 12.04 LTS-based Linux distribution for the Zynq-7000) to eventually send out the data over the internet. I'm having a bit of difficulty understanding how to correctly implement the design in Vivado (2014.4) which is why I'm here. I'm trying to use as many standard Xilinx or Digilent IP cores as possible to make the design straightforward since I am new to FPGA and Vivado. After wading through tons of documentation, I feel like I have a decent understanding of the general design flow for a video design, but as I said I do not have much experience here so I am looking for someone to hopefully point out my mistakes or point me in the right direction.

My current design uses a DVI2RGB IP core provided by Digilent (found here: https://github.com/DigilentInc/vivado-library/tree/master/ip/dvi2rgb_v1_4) which is then interfaced with the Xilinx Video In To AXI4-Stream IP Core (documentation found here: http://www.xilinx.com/support/documentation/ip_documentation/v_vid_in_axi4s/v3_0/pg043_v_vid_in_axi4s.pdf), which then goes to the Xilinx AXI Video Direct Memory Access (VDMA) IP core (documentation found here: http://www.xilinx.com/support/documentation/ip_documentation/axi_vdma/v6_2/pg020_axi_vdma.pdf). Finally, the output of the VDMA is interfaced with an AXI Memory Interconnect to connect it all to the processing system. I do not want to output the video stream that is being written to memory to a display output such as VGA, simply access the video data in Linux and send it out over the internet.

A few questions:

1. First and foremost, does my thought process for the design outlined above make any sense?
2. Do I need to use the Video Timing Controller and subsequently the Video Timing Controller IP cores for a design such as this? My assumption here is NO since the input is providing the clock (which in Vivado is being provided to the Video In To AXI4 and VDMA cores), and nothing is being outputted.

3. The DVI2RGB IP Core takes in TMDS as its input. Do I simply create ports labeled TMDS_Clk_p etc and connect to the input of the IP core? How does Vivado know (and subsequently, how does the board know) those ports I created are supposed to be for the HDMI input port?

4. Assuming my design works and I can successfully write the inputted video stream into memory using the VDMA, is the Xilinx Linux VDMA Driver (found here: http://www.wiki.xilinx.com/DMA+Drivers+-+Soft+IPs) my best bet for accessing the data in the VDMA in Linux? Or is Video4Linux2 (V4L2) something that I should be using here? I've read that V4L2 has compatibility with VLC which seems like a convenient way to then stream the video data over the internet.

Additionally, I was able to import an EDK HDMI_RX IP core into Vivado that is used in a Digilent GoPro Video Filtering Project (found here: https://github.com/LariSan/Digilent-Maker/tree/master/Zybo/zybo_video_demo)Should I be attempting to use this core instead of the DVI2RGB core? I chose the DVI2RGB because it was designed for Vivado rather than EDK, so I assumed it would be easier to use. I would eventually like my design to incorporate audio as well though, which I know DVI doesn't do.

Comments, criticism, advice, help; whatever you've got, it is very welcome here! Anything to steer me in the right direction. Sorry for the long post guys, I've always been a bit verbose I'll attach a screenshot of my Vivado block design to hopefully illustrate some of the things I mentioned about my design. http://i.imgur.com/rdXtuOf.png

Thank you,
Chris
 

[digicloud14]

Hey Run,

The GoPro Project found here https://github.com/LariSan/Digilent-Maker/tree/master/Zybo/zybo_video_demo does exactly what you're trying to do. It takes in HDMI input and forwards it to the VGA for display. Instead of the DVI2RBG Core, it uses the HDMI_RX Core mentioned above, but they are almost identical. The project is in EDK however, and not Vivado, but a look at the source files could possibly answer some of your questions. I'm not exactly sure about the timing constraints, but Jieming above seems to suggest that in his design the timing constraints failed but the video still displayed anyway. Sorry I can't help you more, I'm in a similar position, still trying to figure everything out! Best of luck, come back and update here if you figure it out, I'd love to see the results. And I'll do the same.

Regards,
Chris

[Run Yu]

Hey guys,

I am working on a same kind of project, trying to use the dvi2rgb ip mentioned. I am trying to get input from the HDMI port and display that through the VGA. I am pretty new to Zybo/Vivado 2014.4 and HDMI stuff so I come up with the following questions:

1. I am trying to set the output to be 720p which means I need a ~75MHz pixel clock from the dvi2rgb ip and the Refclk is set to 200MHz. Does it mean that I need to constrain the TMDS clock to 75MHz on the dvi2rgb.xdc & dvi2rgb_ooc.xdc files? I did the calculation and comes up with a change on the xdc file: "create_clock -period 13.334 [get_ports TMDS_Clk_p]". And actually I am not sure how to use those xdc files. Do I need to also include them to the "constraints" with the zybo board constraint? 

I did so but it keeps giving me the following critical warnings:

[Common 17-55] 'set_property' expects at least one object. [dvi2rgb.xdc":7]

(line on xdc file: set_property IODELAY_GROUP dvi2rgb_iodelay_grp [get_cells DataDecoders[*].DecoderX/InputSERDES_X/InputDelay])

 

[Common 17-55] 'set_property' expects at least one object. [dvi2rgb.xdc":8]

(line on xdc file: set_property IODELAY_GROUP dvi2rgb_iodelay_grp [get_cells TMDS_ClockingX/IDelayCtrlX])

 

[Vivado 12-1387] No valid object(s) found for create_clock constraint with option '-objects [get_pins RefClk]'. [dvi2rgb_ooc.xdc":2]

(line on xdc file: create_clock -period 5.000 [get_pins RefClk])

 

 

 

2. If that's not the way to use the xdc files, what that should be?

3. Also, do I need to do something special to the DDC_SCL_I and DDC_SDA_I? I basically just connect them to ports.

4. Last I just tie HPD to VDD, and OUT_EN to GND. Is that OK?

I could generate the bitstream file but as it is up the the zybo using Adept, not any signal comes out from the output of the dvi2rgb module (I mapped PixelClk, locked, HS and VS to the LEDs so I could probe the frequencies but all of them are low).

Thank you very much for any help and suggestions!

 

Run

[digicloud14]

Hey Jieming,

Thank you very much for the reply, the information is very useful to me. Good to know that I am on the right track with the design! Also, thanks for clearing up point #3 for me, that was a big help, and also for providing the TRD reference. I'm sure I'll have more questions, but for now I'll continue working with the information you provided and will report back here soon! Once again, thank you very much!

Chris

[lijieming]

Hi Chris,

It's so happy to see your post since I am just finished a prototype project that very similar to yours except the video will not transmit by eth but being processed on board.

based on my experience I give the following answers to your ques:

1.You thought is absolutely right (my project worked well now just based on this architecture)

2.No VTC is needed at the final stage. But it's strongly recommend you add a VTC during debugging. During my experiment I find out even all of the video source I used marked as "1080p 60p", the video timing is still varies very much due to different recording product and brand.

3.Both the DVI2RGB core and the hdmi_rx core you mentioned before in the "instructables" project works. In fact if you go through the code of the two core you may find out they are almost the same. However (PAY ATTENTION HERE), in vivado, inout port no longer automatically being synthesised to a single port. you have to make a little change at the top level module of the core like

HDMI_SDA <= HDMI_SDA_O when HDMI_SDA_T = '0' else 'Z';
    HDMI_SDA_I <= HDMI_SDA;

of course for the DVI2RGB core you also need to add hdmi support pin (HPD, OUT_EN) but if you go through the hdmi_rx core you'll find the logic of them is really simple There is still something need to care, In the DVI2RGB core's documentation, it says clearly that the input clock should be constraint based on the specific chip. the hdmi_rx core only support 720p video source and DVI2RGB core support up to 1080p video source but the ZYBO is using XC7Z010 -1 chip the MAXBUIO is 600MHZ. 1080p 60p needs 148.5MHZ pixel clock that is around 750 MHZ bit clock. That means if you want to implement the 1080p decoder, the timing requirement will sure fail. But in my experiment. even thought the design fail to meet timing constrains. The 1080p video from my Macbookpro's video card can still be recognised correctly (However the 1080p video from GoPro's hdmi can't be decoded correctly).

4.In my project, the VDMA driver is used, you can take the Zynq Base TRD 2014.4 as a really good reference. All the driver configuration and usage examples has been included in it.

OK, In the final, speaking frankly, It's not an easy road (for developing such a project). you'll meet tons of issues and need to read tons of docs(datasheets userguides refApps) later. Feel free to post any further questions here so as to see if I could give you any help.

 

Jieming