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shodan

Any tutorial for making a working AXI Memory Mapped Master from custom IP?

Question

Hi,

I want to create an AXI Memory Mapped Master from a custom IP which can read/write off-chip memory. I would like to use this IP in my Vivado block design.
Target platform is: Nexys4DDR board with xc7a100tcsg324-1 FPGA. I use Vivado 2014.4 under Win7 64 bit.

 

I have made the Gettig started with Microblaze guide (https://reference.digilentinc.com/nexys4-ddr:gsmb). Everything went fine, now I have a Vivado block design with Microblaze, Uart, MIG, and some other peripherals. I have also set the master.xdc file, and I can generate the bitfile. SDK template tests (hello world, memory test) also passed successfully.

 

I have a custom made IP, from which I would like to make an AXI MM Master peripheral, and I want to control (read/write) the DDR2 memory from my custom made IP.

I have created a new AXI4 peripheral with the Create or Package IP wizard in Vivado. I have choosen the following interface:
Interface Type: Full
Interface Mode: Master
Data Width (Bits): 32

After clicking Finish, Vivado creates a new peripheral in which I can intantiate my custom IP. However this generated myip_v1_0_M00_AXI.vhd looks a little bit hard to understand for me. I haven't even find any Read/Write ports amongst the interface ports. Basically what do I need to control from my custom IP? I assume the M_AXI_AWADDR, M_AXI_WDATA, M_AXI_ARADDR and M_AXI_RDATA ports for address and data, but what about read/write etc?

I have found tons of tutorials on the web about how to make an AXI Lite Slave interfaced IP, but I couldn't find any reference designs for AXI Memory Mapped Master.

Could you please post me some examples or helping by making comments in my file attached?

Thanks!
Shodan

Edited by KaitlynFranz

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There is a pcore for the multiplexing a shared memory bus between three memories for Nexys3 board (you can find it here, and look inside Nexys3_AXI_BSB_Support/lib/Digilent/pcores/d_shared_mem_bus_v1_00_a). Now this core only presents to the system processor as a memory mapped slave device, meaning that besides having the virtual addresses with which you access virtual registers inside the core it also has a region of addresses that corresponds to the actual memory device.

This was done for EDK and uses a module, from inside the axi_lite_ipif library, that did a translation from the AXI4-Lite interface into a more readable one (look into the source files of the Nexys3 BSB). You could use this as a starting point but 

the interface that you want to implement could be a bit complex if you want to support burst read/writes.

If the design allows you I would suggest instantiating MIG and a DMA core that has for reading/writing into the memory streaming interfaces (AXI4-Stream). The implementation of such core is far easier.

 

Mihaita

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