Vivado Errors while running microblaze intro nexys 4 ddr

[gnicholls]

Hello,

 

I am following this tutorial for microblaze for the nexys 4 ddr:

https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze/start?redirect=1

I am getting an error for the mig_7_series... generation that is outlined when I try to generate the bitstream in step 14. It looks like it is pulling the mig from Xilinx's core generation, is it supposed to be using the mig from the nexys 4 ddr files instead? Here is my error output:

Another thing to note, I have a space in the directory path, is that the issue possibly? It is not complaining about anything else though. I have also verified that the file it "can't find" is actually there and has contents. I'm running Vivado 2017.4 WebPack, but I can't imagine this would cause issues for a Xilinx IP core, maybe for IP cores from Digilent.

INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_uartlite_0 .
error deleting "C:/Users/Glen Nicholls/Desktop/fpga_dev/boards/nexys_4_ddr/proj/microblaze/microblaze_intro.srcs/sources_1/bd/microblaze_intro/ip/microblaze_intro_mig_7series_0_0/microblaze_intro_mig_7series_0_0\example_design\rtl\traffic_gen\mig_7series_v4_0_cmd_prbs_gen_axi.v": no such file or directory
CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2017.4/data/ip/xilinx/mig_7series_v4_0/xit/synthesis.xit': error deleting "C:/Users/Glen Nicholls/Desktop/fpga_dev/boards/nexys_4_ddr/proj/microblaze/microblaze_intro.srcs/sources_1/bd/microblaze_intro/ip/microblaze_intro_mig_7series_0_0/microblaze_intro_mig_7series_0_0\example_design\rtl\traffic_gen\mig_7series_v4_0_cmd_prbs_gen_axi.v": no such file or directory
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'mig_7series_0'. Failed to generate 'Synthesis' outputs: 
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'mig_7series_0'. Failed to generate 'Synthesis' outputs: 
ERROR: [BD 41-1030] Generation failed for the IP Integrator block mig_7series_0 
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_mig_7series_0_81M .

[gnicholls]

I realized my design entry was VHDL and this CAN be supported with the MIG, but ONLY from the top level/wrapper. After scrapping my design and ensuring design entry was Verilog, I was able to fix this issue. I was not able to get the suggestions from Xilinx's AR regarding VHDL design entry to work.

[jpeyron]

Hi @gnicholls,

I am glad to hear you were able to get this working. I also wanted to point out that having a space in the path name can cause issues with Vivado/sdk.

thank you,

Jon

[gnicholls]

On 1/8/2018 at 5:08 PM, jpeyron said:

Hi @gnicholls,

I am glad to hear you were able to get this working. I also wanted to point out that having a space in the path name can cause issues with Vivado/sdk.

thank you,

Jon

Thank you for that, I also ran into this issue, but caught it pretty quick since I saw it a while back while looking at some forums. Vivado didn't complain about the path, but SDK most certainly did!