arty Arty Microblaze 2016.4 Project Upgrade to Vivado 2017.4

[RFI]

Hello.

I have developed a Microblaze project based on a Digilent Vivado 2016.4 project for the Arty board that I downloaded a year ago. (microblaze server I believe).

Everything works in Vivado 2016.4, I can go through the entire implementation to bitstream and SDK export.

When upgrading to Vivado 2017.4, I get these errors referring to some encrypted files.

 

 

In reference to error [Synth 8-5809]

I have found this not-to-helpful answer record, referring to FLIT width in an XHMC IP that I dont think is eve nin the project, with no information on how to change it.

https://www.xilinx.com/support/answers/68421.html

 

 

Regarding the second error [synth 8-285]

I found this, which claims the problem was in 2016.2, but still appears, so I am skeptical of this solution. Was the default changed back to OOC per IP with 2017.4?

I am not sure what generate_target means or does, or when it is processed in the GUI workflow. So I am not sure when to do this in the workflow or what it will do.

 

 

https://www.xilinx.com/support/answers/68238.html

In Vivado 2016.3 there was a change to the default BD generation mode. The default was changed from Global to Out of Context (OOC) per IP.

You will not typically see this problem when migrating an existing project because the migration script will maintain the existing generation mode setting. However, in a scripted flow where the entire project or design is being recreated, the new default settings would apply unless explicitly changed.
Additionally, the "OOC per IP" BD generation is not allowed in non-project mode. 

Therefore, starting in Vivado 2016.3, if you are using a scripted non-project mode, you will need to set the BD generation back to global.

To do this, set the synth_checkpoint_mode to None (Global synthesis) before generating targets.

For example:

set_property synth_checkpoint_mode None [get_files ./proj.srcs/sources_1/bd/my_bd/my_bd.bd]

generate_target all [get_files ./proj.srcs/sources_1/bd/my_bd/my_bd.bd]

 

 

Can someone assist me in this upgrade? I imagine Digilent will be upgrading their example projects at some point. Now would be a great time!

 

Thank you!

 

 

 

 

[jpeyron]

Hi @RFI,

I know we will be upgrading a lot of our projects from Vivado 2016.4  to Vivado 2017.4 in the near future. I have forwarded your thread to our content team.  if we run into this issue we will share on this thread how we resolved it. In the mean time i would suggest to reach out to xilinx support here.  Looking through some of the xilinx forum threads I did see some mention of making sure the ips were upgraded as a possible reason for these errors. 

thank you,

Jon 

[RFI]

Thank you for your reply @jpeyron.

I look forward to the upgrade, I am wondering if you might request the content team to attempt a quick upgrade attempt of the Arty microblaze project to see if something quick and obvious can be determined, if there is something obvious that I did wrong, or if they have the same issue. 'Near future' is rather indeterministic, and I need to move on with development. I do not know if it is worth waiting for, a prod may accelerate the pace. I am quite sure that I did upgrade all of the IP. Meanwhile I will do as you suggest and query xilinx. Thanks again.

[jpeyron]

Hi @RFI,

The engineer in our content team that handles the upgrading of our projects has been out sick most of this week. So with that in mind, I made the echo server for the Arty A7 in vivado 2016.4 using the getting started with microblaze servers tutorial and then opened it in Vivado 2017.4. I choose to have vivado upgrade the project from the initial popup. Once the project loaded I clicked on Report IP status and I upgraded/generated the IP cores there. I then generated a bitstream without issue. Let us know if after following this process you still are having issues.

thank you,

Jon