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Vivado synthesis dismantles design that elaborates & simulates correctly


Hey everyone! I'm new to the forum (and fairly new to VHDL as well), and I was hoping you could help me with a problem. :)

I have a project that I'm working on in Vivado (currently it's just some of the inner-workings of a CPU in development), and I'm trying to implement a container that helps me test the design on my FPGA board (Spartan 7 on a Digilent Arty-S7).

The top-level module routes the clock input and reset button input on the FPGA in to the design (inverting the reset button input from active-low to active-high in the process), and routes a 4-bit vector out from the design to 4 LEDs on the board. The purpose is to monitor the high nibble of a 32-bit ALU calculation using the LEDs on the Arty board.

The design works under behavioral simulation, and it elaborates correctly (see attached schematic of the elaborated design).

However, when I synthesize the design, it is reduced to almost nothing -- with the clock and reset pins routed nowhere, and the LED pins routed to some buffers connected to ground. The entire internals of the design are removed (see included schematic of the synthesized design).

Can anyone help me figure out why this is happening?

Here are the sources of the upper levels of the design, and the relevant constraints that I've applied for the FPGA board:




-- pindelivery.vhd
-- Routes package pins to logical units

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

use work.cpu1_globals_1.all;

entity pindelivery is
Port ( clk_in : in STD_LOGIC;
rst_in : in STD_LOGIC;
leds_out : out STD_LOGIC_VECTOR (3 downto 0));
end pindelivery;

architecture behavioral of pindelivery is

component topLevel_debug
port (clk : in std_logic;
rst : in std_logic;
led_out : out std_logic_vector(3 downto 0));
end component;

signal rst_out : std_logic := '0';


rst_out <= not rst_in;

tld1 : topLevel_debug
port map (clk => clk_in,
rst => rst_out,
led_out => leds_out);

end behavioral;




-- topLevel_debug.vhd
-- Top-level module for debug

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

use work.cpu1_globals_1.all;

entity topLevel_debug is
port ( clk : in std_logic;
rst : in std_logic;
led_out : out std_logic_vector (3 downto 0));
end topLevel_debug;

architecture behavioral of topLevel_debug is

component controlTest
port (clk : in std_logic;
rst : in std_logic;
r0_highnibble : out std_logic_vector(3 downto 0));
end component;


cpu1 : controlTest
port map (clk => clk,
rst => rst,
r0_highnibble => led_out);

end behavioral;







## Clock signal
set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { clk_in }]; #IO_L13P_T2_MRCC_15 Sch=uclk
create_clock -add -name sys_clk_pin -period 83.333 -waveform {0 41.667} [get_ports { clk_in }];

## LEDs
set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { leds_out[0] }]; #IO_L16N_T2_A27_15 Sch=led[2]
set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { leds_out[1] }]; #IO_L17P_T2_A26_15 Sch=led[3]
set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { leds_out[2] }]; #IO_L17N_T2_A25_15 Sch=led[4]
set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { leds_out[3] }]; #IO_L18P_T2_A24_15 Sch=led[5]

## Reset button
set_property -dict { PACKAGE_PIN C18 IOSTANDARD LVCMOS33 } [get_ports { rst_in }]; #IO_L11N_T1_SRCC_15

## Configuration options, can be used for all designs
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]

set_property INTERNAL_VREF 0.675 [get_iobanks 34]



Any assistance would be much appreciated!


Curt Pehrson



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UPDATE: I figured it out. An error I made deeper in the design led to the output signal effectively never being set to any value except "0000", hence the trimming of logic.


Thanks for your time!



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