Unable to add modules to designs

[Android]

Hi again,

i need some more help.

I am unable to add my HDL modules to any block design I have created by following the tutorials.

I have tried both create new project with and without specify sources. I am able to add the sources (either initially or later), but when I try to Add module, there are no modules to select. If I go to Sources/Heirarchy/non-module files and select one of the verilog files that I added, then right-click, the 'Add module to block design' option is greyed out.

I am stuck here. Please advise.

Thanks,

AN

[Android]

Just a dumb thought ... Do the source files need to be added one-at-a-time when doing 'add sources'? These were added by selecting all.

AN

[jpeyron]

Hi @Android,

I found a xilinx forum thread that states that the add a module function only works with VHDL and Verilog and not System verilog. I am in the middle of testing something for another customer, when I am done I will try adding these files to verify. 

cheers.

Jon

[Android]

Another typo, Im sorry. Should have tried it in my ncsim env first.

'timescale directives are optional.

Also functionality obviously wrong, but irrelevant.

But, here's my screen capture after adding the less dubious file i have attached. Top module name is giving me fits. design2_wrapper.v and design2.v keep ending up in the wrong places.

I don't understand your statement: " I guess you could try copying the file into a Vivado project that doesn't use IPI to check them before you go to add the module."

Should I be bothering xilinx and not you about this?

Andy

 

 

 

prot_mux2.v

[artvvb]

@Android

Adding all sources at the same time should be fine. The issue that I see is that Vivado is detecting some kind of syntax error in the files - hence categorization under "Non-Module Files". This might be some form of unsupported SystemVerilog syntax (I am unfamiliar with systemverilog). When I try to import capt_wrapper (in a 2017.4 project), I am seeing a syntax error on line 60 (input <clock>, //  (required)) that could be causing issues. The "Referencing RTL Modules" section of Xilinx UG994 starting on page 159 lists a few other reason why the sources might not be showing up in the list (although that particular document won't tell you why there might be syntax errors).

Thanks,

Arthur

[Android]

Yeah, that thing on line 60 of capt_wrapper.v was a direct copy from the user manual, and is apparently a note to me the user, and not part of the attributes that need to be added.

But having tried it with the the attributes fixed, I get the same result and the file ends up in non-module sources.

Attqached is the fixed file.

AN

 

capt_wrapper.v

[artvvb]

Are any sources in the hierarchy underneath capt_wrapper.v not found? Other than commenting out that line, the other thing I had to do to make the capt_wrapper module appear was comment out the instantiation of prot_mux2 (line  197). Do you have access to this file? You don't need to provide it to us, but if you don't have it, then you will not be able to add the module. The screenshot below shows my hierarchy tab with only line 60 commented out.

Thanks,

Arthur

[Android]

Good catch.

But why can't I see the error that's being raised, but you can?

It's not correct for you to be debugging my simple compile issues.

AN

[Android]

Sorry for being so terse.

Here is a screenshot.

As you can see there is no indication to me (the admittedly new user) that there are compile issues with the file I am adding.

Am i looking at the wrong window? 

How should I know to look at the log for errors, and where  would that log be?

AN

 

 

[artvvb]

@Android

You are looking at the correct window. A couple of GUI tips that might help:

In the Sources pane, on the right side of the toolbar there is the orange exclamation point with the number 4 next to it. If you click on that it will open up the messages tab in the pane at the bottom of the screen that currently is displaying the TCL console. This will show the critical warnings, which (hopefully) will be hints that there are syntax errors.

If you right click anywhere withing the Sources pane, one of the options is to "Refresh the Hierarchy", which will force vivado to make sure that it is showing everything as it should be. I would try doing this before anything else.

[Android]

Thank you so much for your help, and sorry to drag you into this elementary problem of compilation.

I had asked about these 4 warnings earlier, because they are beyond vague, and your response confirmed my suspicions. 

It's incredible to me that such a severe error wouldn't be flagged as such.

I should have taken this up with vivado support, but thanks again for steering  me right.

AN

[Android]

Hi Arthur,

I'm back on this. Still, I find it impossible to add any RTL source files and then use the modules in my block design.

When I create my design_2_wrapper.v it always shows up under non-module files.

Same with the verilog files I add using add sources.

Always I get the severe warnings below. Where are the details of the problem? Is there a detailed log that I can read? 

Attached is a simple verilog test file. This should not have compilation or heirarchy errors. I must have a screwed up env.

• [filemgmt 20-2001] Source scanning failed (launch error) while processing fileset "sources_1" due to unrecoverable syntax error or design hierarchy issues. Recovering last known analysis of the source files.

• [filemgmt 20-2001] Source scanning failed (launch error) while processing fileset "sim_1" due to unrecoverable syntax error or design hierarchy issues. Recovering last known analysis of the source files.

prot_mux2.v