Unable to add modules to designs

[Android]

Hi again,

i need some more help.

I am unable to add my HDL modules to any block design I have created by following the tutorials.

I have tried both create new project with and without specify sources. I am able to add the sources (either initially or later), but when I try to Add module, there are no modules to select. If I go to Sources/Heirarchy/non-module files and select one of the verilog files that I added, then right-click, the 'Add module to block design' option is greyed out.

I am stuck here. Please advise.

Thanks,

AN

[Android]

Hey Jon, thanks for the reply.

I tried to attach the project, but it's way too big, 45 MB, and the forum site limits attachments to 1.95 MB.

I used my code to implement the steps in the intc_example1 SDK project that I found in SDK somewhere, and my code is nearly identical and works perfectly with the phony (software generated using an XIntc register write) interrupt that they do.

In the microblaze, there should (I hope) be an internal register where the status of the 32-bit address input and the 1-bit INT (or IRQ, or whatever they call it) input to the CPU can be read.

If so, then I should be able to step through in a debug session and see if those ports are doing what they're supposed to.

But this toolset and environment as well as the hardware designs are all brand new to me, so there is so much to learn on the way to getting a stupid interrupt.

[jpeyron]

Hi @Android,

We would suggest that you reach out to Xilinx support here. Maybe a re-install of vivado might be in order?

thank you,

Jon

[Android]

Hi again,

Indeed a reinstall of Vivado finally was the only way out from under this.

Now, I have my verilog IP and my block design all stiched up and synthesized error and warning free.

Final step before proceeding, I need to control with my IP, multiple I/O pins on a clock-by-clock basis, including both pad-direction ad pad data.

Can you point me to a tutorial or a UM section that explains how to connect this up? Is there a prepackaged connector IP available for this purpose?

Thank you again for your patience.

AN

[jpeyron]

Hi @Android,

Glad to hear that re-installing vivado worked. I would suggest looking into the Pmod Bridge and seeing if that would work for you.

cheers,

Jon

[artvvb]

The Pmod bridge is primarily a remap from one of a couple of different built in interfaces into the Pmod interface used by our board files. If you configure both top and bottom rows to use the GPIO interface, you can expand the interface and manually connect other IPs to the gpio_i, gpio_o, and gpio_t ports. This can be a little tedious and hacky, but it should work fine.

Thanks,

Arthur

[Android]

Thanks. I got it working  different way.

I have one interrupt controller with 2 interrupts (uart and my design).

Can you point me to simple example C code to setup the interrupts?

Thanks,

AN

[jpeyron]

Hi @Android,

Glad you were able to get your project working. Here is a xilinx forum thread that talks about using interrupts as well as has an example.

thank you,

Jon

[Android]

Hello again,

I am a failure. I can't get interrupts working. I followed the example as closely as possible, given the differences.

Xilinx support is ignoring me.

Maybe you guys can get me out of this hole ...

I have a block design with 1 interrupt controller, using only 1 interrupt source, which comes in from my external RTL module.

Am I missing something stupid and obvious that everybody else knows about?

Here is my super-simple test code:

 

 

 

Spoiler

 

void ct20_ISR (void) {

  xil_printf("In the ISR now (finally).\n\r");

  LPC_CAPT->STATUS = 0x7F;                      // Clear all interrupt flags

  int_flag = 1;                                 // Set handshake for main, then return

}

 

 

int main()

{

 

    // Declare and initialize the pointer to the (only) instance of the XIntc driver

    XIntc * IntcInstancePtr = &InterruptController;

    

    init_platform();

 

    // Initialize the interrupt controller driver

    XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);

   

 

    // Connect ct20_ISR to the XIntc handler (this is the only instance, no callback)

    XIntc_Connect(IntcInstancePtr, 0, (Xil_ExceptionHandler)ct20_ISR, 0);

 

 

    // Enable the interrupt vector at the XIntc controller (Is '0' correct here too?)

    XIntc_Enable(IntcInstancePtr, 0);

 

    // Start the XIntc controller

   XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);

   

 

    // Initialize the exception table

    Xil_ExceptionInit();

 

    // Register the XIntc controller's actual handler with the exception table

    Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler)INTC_HANDLER, IntcInstancePtr);

 

    // Enable non-critical exceptions

    Xil_ExceptionEnable();

 

    

 

    // Now the application-specific stuff (this will start the machine and assert the IRQ)

    int_flag = 0;

    LPC_CAPT->CTRL |= 2<<0;                              // Start it

 

    while(int_flag == 0) { // Wait for handshake from ISR

    }

 

    xil_printf("Back in main now.\n\r");

    while(1);

 

 

    cleanup_platform();

    return 0;

}

 

 

[jpeyron]

Hi @Android,

I have not worked with interrupts in microblaze very much. I did not see anything wrong with the SDK code specifically. Here is a forum thread about interrupts.  Here is a link that discusses using microblaze and interrupts. Can you attach your project?

thank you,

Jon

[artvvb]

I am not sure why actual syntax errors aren't showing up for you. I guess you could try copying the file into a Vivado project that doesn't use IPI to check them before you go to add the module.

The attached file has "do" instead of "d0" on line 11. It is also missing a "`timescale 1ns / 1ps" line at the top of the file (though this may not be required).

As a bit of a sidenote, the assign statement on line 11 is a three input and, not a mux. I would expect "assign z = (d0 & ~s0) | (d1 & s0);" or other equivalent syntax.

Thanks,

Arthur

[Android]

Another update:

With a debug session running I see that the IE bit in the MSR is NOT set after all that screwing around with configuring the AXI INTC correctly.

Searching for "how do I set the IE bit in the microblaze MSR" produced no hits on either Xilinx site search or Google. Can you imagine?!

So ... how DO I set the IE bit in the microblaze MSR (using C, or C with embedded assembly)?

Thanks,

AN

[JColvin]

Hi @Android,

I'm personally not experienced with the interrupts in Microblaze either, but it looks like there may be a function that does it according to this, microblaze_enable_interrupts(). It is working with EDK though so I don't know how things may have changed now.

Thank you,
JColvin

[Android]

Hey John, thanks for your response.

Yes you are correct, microblaze_enable_interrupts() is what I am using. If my manager would stop pulling me away, I wouldn't forget what I already know when I get back to this.

Another my-dumb: microblaze_enable_interrupts() is working correctly. I saw the MSR getting the value 0x2, when I expected 0x40000000, and since bit 1 is reserved, my reaction was WTF? I dumbly forgot that microblaze is big-endian (why, why, why?).

So ... Interrupts ARE enabled at the microblaze's IRQ input, and the problem is at the XINTC.

By the way, for those of you out there in television land who were wondering, with only 1 interrupting device in a microblaze system that uses the AXI Interrupt controller, below is all that one must do to use a fast interrupt for your device:

First, Compile your ISR with the following pragma, so that the saving and restoring of context is handled by the compiler, and the requirement for an intermdediate handler at address 0x10 is removed.

__attribute__((fast_interrupt)) void my_ISR(void) {blah; blah; blah;}

Then, in your main routine ...

    *xintc_ivar = (unsigned int)(&my_ISR); // Supply the address of the ISR for the device on slot 0
    *xintc_imr = 0x1;                                   // Configure the interrupt mode for slot 0 as a fast interrupt
    *xintc_ier = 0x1;                                    // Enable slot 0
    *xintc_mer = 0x3;                                  // Set the 2 bits in Master enable (no more fakey hw ints, real ones only)
    microblaze_enable_interrupts();           // Enable the CPU to respond to its IRQ

 

I will need to simulate in order to get to the bottom of this.

Questions (sorry for the long list)

A. When I'm debugging my system on the Arty board, can I get the debugger to generate a reset?

B. What is the difference between disconnect and terminate?

C. Why does relaunch reset the BD but not my RTL?

D. How can I get a full system pin-resetting, or power-cycling the Arty board and starting over?

E. Can I recompile the software and reset without leaving the debugger? 

 

Questions about the simulator before I dive in:

1. In the Vivado simulation environment will I be able to probe inside my RTL design which is external to my BD?

2. If the answer to (1) is no, then if I package the IP and put it inside the BD, will I be able to probe inside it?

3. Does simulating the block design reference RTL? If so, where is it located?

 

[jpeyron]

Hi @Android,

I unfortunately do not have that level of knowledge with Vivado/SDK. Here is the SDK ,Vivado,  synthesis, simulation user guides that should be helpful.  Also xilinx support would be able to better answer these type of questions about their software. I am sorry for the inconvenience.

thank you,

Jon

[Android]

Hi jon

Hey John, thanks for your response.

Yes you are correct, microblaze_enable_interrupts() is what I am using. If my manager would stop pulling me away, I wouldn't forget what I already know when I get back to this.

Another my-dumb: microblaze_enable_interrupts() is working correctly. I saw the MSR getting the value 0x2, when I expected 0x40000000, and since bit 1 is reserved, my reaction was WTF? I dumbly forgot that microblaze is big-endian (why, why, why?).

So ... Interrupts ARE enabled at the microblaze's IRQ input, and the problem is at the XINTC.

By the way, for those of you out there in television land who were wondering, with only 1 interrupting device in a microblaze system that uses the AXI Interrupt controller, below is all that one must do to use a fast interrupt for your device:

First, Compile your ISR with the following pragma, so that the saving and restoring of context is handled by the compiler, and the requirement for an intermdediate handler at address 0x10 is removed.

__attribute__((fast_interrupt)) void my_ISR(void) {blah; blah; blah;}

Then, in your main routine ...

    *xintc_ivar = (unsigned int)(&my_ISR); // Supply the address of the ISR for the device on slot 0
    *xintc_imr = 0x1;                                   // Configure the interrupt mode for slot 0 as a fast interrupt
    *xintc_ier = 0x1;                                    // Enable slot 0
    *xintc_mer = 0x3;                                  // Set the 2 bits in Master enable (no more fakey hw ints, real ones only)
    microblaze_enable_interrupts();           // Enable the CPU to respond to its IRQ

 

I will need to simulate in order to get to the bottom of this.

Questions (sorry for the long list)

A. When I'm debugging my system on the Arty board, can I get the debugger to generate a reset?

B. What is the difference between disconnect and terminate?

C. Why does relaunch reset the BD but not my RTL?

D. How can I get a full system pin-resetting, or power-cycling the Arty board and starting over?

E. Can I recompile the software and reset without leaving the debugger? 

 

Questions about the simulator before I dive in:

1. In the Vivado simulation environment will I be able to probe inside my RTL design which is external to my BD?

2. If the answer to (1) is no, then if I package the IP and put it inside the BD, will I be able to probe inside it?

3. Does simulating the block design reference RTL? If so, where is it located?

 

[Android]

OK, no problem. Thanks for the user guide chapters. I'll bother Xilinx at this point, although you guys are WAY more responsive and helpful.

AN

[Android]

Hi again,

I notice that I have two versions of Arty-Master.xdc floating around, both say on line 1:

## This file is a general .xdc for the ARTY Rev. B

but they are different with regard to the ck_io[]-to-package-pin assignments, at least.

Will you point me to the latest-and-greatest? My board is Rev. C.

Thanks

AN

[jpeyron]

Hi @Android,

The Arty-A7-35-Master.xdc and the Arty-Master.xdc are the same besides one says rev b and one says rev d. The Arty-Master.xdc will be removed in the near future since the Arty-100t is coming out.  Either xdc will work for you.

thank you,

Jon

[Android]

Hi,

I saw that too, and tried also with Verilog only, with the same result.

In some thread I also found that the top-level module must be in Verilog, but the sub-modules can be SystemVerilog.

I'll await for your results.

Thanks, AN

[jpeyron]

Hi @Android,

What version of vivado are you using? Here is a forum thread that discusses using the add a module process(add a block). To use the add a module you need to have a block design open and then right click on empty spot in the block design and the add a module should be available.  I have attached some screen shots showing this. 

cheers,

Jon

[Android]

Hi,

I am using Vivado v2017.3.

I am doing exactly what you say, and just as in your screen shot, my verilog files that i have added will not show up under the Add a module, RTL module type under search.

In capture 1 the verilog files appear under non-module files.'

If i select the verilog file its add module to block design is greyed out (see untitled.png)

There are 4 critical warnings that always come up, see capture 2. This may be the problem, but i have no idea what they are or how they can be fixed.

AN

 

 

 

 

[jpeyron]

Hi @Android,

You need to click on add sources and add the HDL file you want to use and then follow right click on the block design and click add module. I have attached a screen shot where i added AD1.vhd to the project and it now shows in the add to module choices. The link I posted above also has a project that has a hdl file connected using this process.

cheers,

Jon

[Android]

Hi,

Again ... I Have Done That.

The added HDL source files do not show up as available as modules to add to the block design.

AN

[jpeyron]

Hi @Android,

Please post the hdl source files and I will see if I can get them to show up in my project.

cheers,

Jon

[Android]

Hi,

Files attached.

The top level of the IP I am trying to add is capt_wrapper.v.

The submodules are  all defined in the *.sv files.

AN

capt_engine.sv

capt_regs_cdc.sv

capt_sync.sv

capt_wrapper.v

ct_filters.sv

ct_sorter.sv