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Unable to add modules to designs

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Hi again,

i need some more help.

I am unable to add my HDL modules to any block design I have created by following the tutorials.

I have tried both create new project with and without specify sources. I am able to add the sources (either initially or later), but when I try to Add module, there are no modules to select. If I go to Sources/Heirarchy/non-module files and select one of the verilog files that I added, then right-click, the 'Add module to block design' option is greyed out.

I am stuck here. Please advise.

Thanks,

AN

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Hi @Android,

What version of vivado are you using? Here is a forum thread that discusses using the add a module process(add a block). To use the add a module you need to have a block design open and then right click on empty spot in the block design and the add a module should be available.  I have attached some screen shots showing this. 

cheers,

Jon

Add_module_1.jpg

Add_module_2.jpg

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Hi,

I am using Vivado v2017.3.

I am doing exactly what you say, and just as in your screen shot, my verilog files that i have added will not show up under the Add a module, RTL module type under search.

In capture 1 the verilog files appear under non-module files.'

If i select the verilog file its add module to block design is greyed out (see untitled.png)

There are 4 critical warnings that always come up, see capture 2. This may be the problem, but i have no idea what they are or how they can be fixed.

AN

 

 

 

 

Capture.PNG

Capture2.PNG

Capture3.PNG

Untitled.png

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Hi @Android,

You need to click on add sources and add the HDL file you want to use and then follow right click on the block design and click add module. I have attached a screen shot where i added AD1.vhd to the project and it now shows in the add to module choices. The link I posted above also has a project that has a hdl file connected using this process.

cheers,

Jon

add_module.3.jpg

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Just a dumb thought ... Do the source files need to be added one-at-a-time when doing 'add sources'? These were added by selecting all.

AN

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Hi @Android,

I found a xilinx forum thread that states that the add a module function only works with VHDL and Verilog and not System verilog. I am in the middle of testing something for another customer, when I am done I will try adding these files to verify. 

cheers.

Jon

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Hi,

I saw that too, and tried also with Verilog only, with the same result.

In some thread I also found that the top-level module must be in Verilog, but the sub-modules can be SystemVerilog.

I'll await for your results.

Thanks, AN

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@Android

Adding all sources at the same time should be fine. The issue that I see is that Vivado is detecting some kind of syntax error in the files - hence categorization under "Non-Module Files". This might be some form of unsupported SystemVerilog syntax (I am unfamiliar with systemverilog). When I try to import capt_wrapper (in a 2017.4 project), I am seeing a syntax error on line 60 (input <clock>, //  (required)) that could be causing issues. The "Referencing RTL Modules" section of Xilinx UG994 starting on page 159 lists a few other reason why the sources might not be showing up in the list (although that particular document won't tell you why there might be syntax errors).

Thanks,

Arthur

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Yeah, that thing on line 60 of capt_wrapper.v was a direct copy from the user manual, and is apparently a note to me the user, and not part of the attributes that need to be added.

But having tried it with the the attributes fixed, I get the same result and the file ends up in non-module sources.

Attqached is the fixed file.

AN

 

capt_wrapper.v

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Are any sources in the hierarchy underneath capt_wrapper.v not found? Other than commenting out that line, the other thing I had to do to make the capt_wrapper module appear was comment out the instantiation of prot_mux2 (line  197). Do you have access to this file? You don't need to provide it to us, but if you don't have it, then you will not be able to add the module. The screenshot below shows my hierarchy tab with only line 60 commented out.

image.png.5fb31b28f9b8deb8fae7089ddc24ec6a.png

Thanks,

Arthur

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Good catch.

But why can't I see the error that's being raised, but you can?

It's not correct for you to be debugging my simple compile issues.

AN

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Sorry for being so terse.

Here is a screenshot.

As you can see there is no indication to me (the admittedly new user) that there are compile issues with the file I am adding.

Am i looking at the wrong window? 

How should I know to look at the log for errors, and where  would that log be?

AN

 

 

Capture.PNG

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@Android

You are looking at the correct window. A couple of GUI tips that might help:

In the Sources pane, on the right side of the toolbar there is the orange exclamation point with the number 4 next to it. If you click on that it will open up the messages tab in the pane at the bottom of the screen that currently is displaying the TCL console. This will show the critical warnings, which (hopefully) will be hints that there are syntax errors.

If you right click anywhere withing the Sources pane, one of the options is to "Refresh the Hierarchy", which will force vivado to make sure that it is showing everything as it should be. I would try doing this before anything else.

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Thank you so much for your help, and sorry to drag you into this elementary problem of compilation.

I had asked about these 4 warnings earlier, because they are beyond vague, and your response confirmed my suspicions. 

It's incredible to me that such a severe error wouldn't be flagged as such.

I should have taken this up with vivado support, but thanks again for steering  me right.

AN

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Hi Arthur,

I'm back on this. Still, I find it impossible to add any RTL source files and then use the modules in my block design.

When I create my design_2_wrapper.v it always shows up under non-module files.

Same with the verilog files I add using add sources.

Always I get the severe warnings below. Where are the details of the problem? Is there a detailed log that I can read? 

Attached is a simple verilog test file. This should not have compilation or heirarchy errors. I must have a screwed up env.

  • [filemgmt 20-2001] Source scanning failed (launch error) while processing fileset "sources_1" due to unrecoverable syntax error or design hierarchy issues. Recovering last known analysis of the source files.
  • [filemgmt 20-2001] Source scanning failed (launch error) while processing fileset "sim_1" due to unrecoverable syntax error or design hierarchy issues. Recovering last known analysis of the source files.

prot_mux2.v

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I am not sure why actual syntax errors aren't showing up for you. I guess you could try copying the file into a Vivado project that doesn't use IPI to check them before you go to add the module.

The attached file has "do" instead of "d0" on line 11. It is also missing a "`timescale 1ns / 1ps" line at the top of the file (though this may not be required).

As a bit of a sidenote, the assign statement on line 11 is a three input and, not a mux. I would expect "assign z = (d0 & ~s0) | (d1 & s0);" or other equivalent syntax.

Thanks,

Arthur

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Another typo, Im sorry. Should have tried it in my ncsim env first.

'timescale directives are optional.

Also functionality obviously wrong, but irrelevant.

But, here's my screen capture after adding the less dubious file i have attached. Top module name is giving me fits. design2_wrapper.v and design2.v keep ending up in the wrong places.

I don't understand your statement: " I guess you could try copying the file into a Vivado project that doesn't use IPI to check them before you go to add the module."

Should I be bothering xilinx and not you about this?

Andy

 

 

 

Capture.PNG

prot_mux2.v

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Hi again,

Indeed a reinstall of Vivado finally was the only way out from under this.

Now, I have my verilog IP and my block design all stiched up and synthesized error and warning free.

Final step before proceeding, I need to control with my IP, multiple I/O pins on a clock-by-clock basis, including both pad-direction ad pad data.

Can you point me to a tutorial or a UM section that explains how to connect this up? Is there a prepackaged connector IP available for this purpose?

Thank you again for your patience.

AN

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The Pmod bridge is primarily a remap from one of a couple of different built in interfaces into the Pmod interface used by our board files. If you configure both top and bottom rows to use the GPIO interface, you can expand the interface and manually connect other IPs to the gpio_i, gpio_o, and gpio_t ports. This can be a little tedious and hacky, but it should work fine.

Thanks,

Arthur

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Thanks. I got it working  different way.

I have one interrupt controller with 2 interrupts (uart and my design).

Can you point me to simple example C code to setup the interrupts?

Thanks,

AN

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