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AXI DMA and Microblaze


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Hello All,

I seem to be having an issue that I cannot quite track down the cause of... My overall goal is that I would like to write ADC samples into DDR memory via a DMA. I am able to DMA samples into the DDR successfully, except that the first couple values in DDR are incorrect. I've noticed that if I aquire some samples, and read the DDR, the first 4 are old samples which seem to update the next time I do an acquisition of ADC samples.  I've also noticed that after the first DMA transfer, if I read the s2mm_length register, it seems to be a few transfers short of what I programmed the transfer length to be.  But if I do another transfer, and all subsequent transfers from then on, they seem to be equal to the length which was programmed.  I initially thought that this was a caching issue (and still may be), but I've since disabled caching in the software. I've also provided an image below of my Microblaze, and to my understanding there is no caching enabled (i've disabled cache when configuring the Microblaze in vivado).  The type of DMA transfer that I am using is just a register direct transfer, not scatter gather.

microblaze_external_mem.PNG.613998078f5cc1d511ca77848db313ea.PNG

 

The M_AXI_DP is connected to an AXI Interconnect, of which the M_AXI port of the interconnect is connected to the S_AXI_LITE port of the DMA. Another interesting thing I've noticed is that, if I do an acquisition of ADC samples, read the DDR starting at address 0, and perform another read of DDR starting at address 0, it looks like the data at address 0 updates, but the following data is the same as the first read. 

 

P.S. I am still new to Digital Design, sorry if I've omitted any crucial information.

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@jpeyron

After looking further into this, I had finally figured out what the issue was but forgot to post what I had found on here. I managed to get the ILA working, and had observed the AXI interaction between the DMA and some of the other IP in my project. What I had found was that the DMA had not be 'setup' with enough time before actual data had been streaming. The AXI DMA Product guide explains it better by this quote: 

Quote

Note: In the absence of any setup (that is, before it is programmed to run), AXI DMA will pull the
s_axis_s2mm_tready signal Low after taking in four beats of streaming data. This will throttle the
input data stream. To have a minimum amount of throttling, ensure that the AXI DMA is set up to run
much before the actual data arrives.

This explains why the first 4 ADC samples I had seemed off, and after those samples the data was good. In the end, I've learned yet again that most questions I have can be answered in these user guides, I just don't have enough experience yet to know where to always look

 

Cheers,

nystflame

Edited by Nystflame
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