FFT issue on ARTY Board

[train04]

Hiii,

 I have some issue with Arty board for finding FFT output ...using MICROBLAZE , I have tried a lot but unable to configure   block diagram using  IP configuration 

please can anybody has solution for this ....how to make IP integrator for finding FFT....

mail id -   shubhamgwl04@gmail.com

[D@n]

@train04,

I can't seem to find a link for the FFT 6.0 core user's guide.  If that's the core you are using, then could you provide a link to the user's guide?  I found v7.1 and v9.0 (axi based).  If you are using the Artix-7, I would expect you would be using v9.0 not v6.0.

Next, if you aren't using any buffering, then you'll want the FFT set up in "pipeline" mode.  This is the mode that accepts a sampled stream as an input and produces a sampled FFT stream as an output.  My guess is that this is your problem right now, and the reason why the trace looks as it does.

There is a delay going through the FFT--I think it's about 3 FFT lengths or so, but it's been so long that I'm not sure anymore.  Be prepared for that.

When you work with a DDS input, you can set the valid line to one.  Be aware that you'll get one sample out per clock as well.  If you are going to be working with an  A/D that will be providing samples at less than full rate (~ 100MHz or so), then you'll want to do something other than connect the valid line to one.  Instead, set it to one for one clock period whenever you expect your A/D will have a valid sample. 

In a similar manner, if the valid signal is perpetually one going into the core, it will also be perpetually one coming out of the core.  You'll need to be able to deal with that data rate.  You'll probably also want to look into how the core signals the start of a new FFT in its output--that'll be important for you as well.

Dan

[D@n]

@train04,

You tell me, are the outputs correct?

The proper way to debug any FPGA-based DSP algorithm is to run the algorithm in both hardware (Arty, although I like using the software emulator Verilator) and software (Octave), and compare the results.  When the results match, you know your hardware algorithm is working.

Dan

[train04]

Thanks @D@n..

I will try to resolve this..... but What about FFT ...and .CSV file that I have send you .......

my FFT output are coming correct or any modification is required.

[D@n]

You might just wish to hold the IFFT in a reset state until the first valid output comes out of the FFT ...

Dan

[D@n]

@train04,

Thanks, that resolves one possibility.  You've still got alignment issues between your FFT and your IFFT.

Dan

[train04]

Hiii    @D@n

I am attaching the same image after zooming it....

my sine wave is looking correct, yeah I know FFT having some issue......may be configuration setting.....In previous post I have written all configuration setting what I am doing, please you check it if any thing I configured incorrect ....

same doubt I also had , about two incoming frequency as IFFT.......

please tell me what improvement is required ..... either I am going in right way or should I start from beginning. 

configuration setting again attached ..

DDS -- 

clock -- 100Mhz

channel -- 1

standard mode

system parameter

sine wave 

frequency 10 Mhz

 

FFT--

channel --1

transform length --2048

50 Msps

clock ----- 100MHz

pipeline ,streaming mode

no run time configuration

block floating point

convergent rounding

natural bit order 

real time

same for IFFT as well.

 

I am also sending a .CSV file of output from  ILA core.

here you can check the data .

shubham.csv

[D@n]

@train04,

I almost missed that you'd sent something to me.  Do me a favor ... when you want to get my attention, type the "@" sign followed by my screen name, "D@n". The forum will then give you a menu with my name on it.  Select my name.  The result should look something like @D@n.   That'll let me know you wrote something that you wanted me to take a look at.

With that out of the way, let's see what we can learn from the image you just posted.

1. Something looks wrong with your DDS output.   If you zoom in on it, does that look like a sine wave?  From here it looks like ... something else, like perhaps you didn't get the bit assignments right--I can't quite tell.  It might be right--I just can't tell at this zoom setting.
2. Judging from the FFT output, it looks like you are getting two impulses out per FFT, one on (hopefully) bin 205 or so and another on bin 1843 or so. 
3. There's a real trick to getting an IFFT to work following an FFT.  It's simple in matlab or C/C++, no so simple in RTL.  In particular, you need to make certain the two are aligned.  From what you are showing above, I'm not certain this is the case.  Were the channels misaligned, bin 205 and bin 1843 might two lose their alignment and become two separate frequencies beating against each other.  That looks like what you have going on here.
4. The impulses coming out of the inverse FFT are puzzling me.  They suggest that you have a touch of a bias going into the IFFT, perhaps your samples aren't centered around zero as you'd like?  Again, I can't tell from here.

One of the things I like to do when debugging FFT's is to pull the (output) sample values into a program where I can examine them--perhaps Matlab or Octave.  You should then be able to take your own FFT (within Matlab or Octave) and compare it with the results you are getting.  Plot both methods on your screen at the same time.  That'll help you "see" visually whether one method has a problem or not.

Dan

[train04]

hii D@n

I am getting something & want to share with you.

I have applied some changes in the IP configuration of FFT IP 9.0 , and I am getting some output beans

so for checking purpose I have implemented IFFT configuration for getting sine wave as output.

but I am still confused something is fishy or went wrong ....I am getting AM modulated wave.

so please can you help me out there I am attaching image of  real time ILA output .

 

configuration setting  ---

 

DDS -- 

clock -- 100Mhz

channel -- 1

standard mode

system parameter

sine wave 

frequency 10 Mhz

 

FFT--

channel --1

transform length --2048

50 Msps

clock ----- 100MHz

pipeline ,streaming mode

no run time configuration

block floating point

convergent rounding

natural bit order 

real time

 

same for IFFT as well.

[train04]

Hii D@n

In previous picture I have noticed that my output of FFT always coming either 0 or 1. did you noticed too.

this means my output is not coming ......b'cos FFT output is not  0 or 1 ... what I have checked in the MATLAB.

 

[D@n]

@train04,

Ahm, yeah, you do have some problems with your setup.

1. If your sample rate an your clock rate are the same, then you can hold the data valid line high.  This is the easiest to debug.
2. If the sample rate is slower than the clock rate, then you are telling the FFT generator that it can have (clock rate / sample rate) clocks to process each sample.  This allows the FFT generator to do things like reusing those expensive multiplies.  The problem, though, is if you provide data to the core on every clock after telling it that your sample rate is slower than your clock rate.  If you do that, you are likely to corrupt the internals of the FFT.  In other words, if you don't know what you are doing then set the sample rate equal to your clock rate to get things to work.  (We can adjust this later--once you have the confidence that the FFT works)
3. The bit-reversed output is something I wouldn't expect most people to use.  As a bit of a background, most FFT's produce a bit reversed output naturally.  This means that (were this an 8-sample FFT) you'd get samples out in the order: 0 4 2 6 1 5 3 7.  If that order looks confusing, then look at it in binary: 3'b000, 3'b100, 3'b010, 3'b110, 3'b001, 3'b101, 3'b011, 3'b111 and read the bits from right to left instead of left to right.  That's what bit reversal is about.  FFT's by nature produce a bit-reversed output.  The problem is that most algorithms people develop want the output in its natural order: 0 1 2 3 4 5 6 7.  While swapping the order isn't difficult, it does require a buffer the size of two FFT lengths and a bit of decoding logic.  While there are a few use cases for a bit reversed output, such as when you only wish to examine a known bin or when you wish to modify the coefficients and then apply an IFFT that accepts a bit-reversed input, the difficulty of using the bit-reversed output really keeps it from being useful.
4. Finally, if you wish to post a picture of a trace ... please label the trace lines something meaningful, rather than probe_0.

Thanks,

Dan

[train04]

HI D@n

I have changed the configuration as you suggest me..... like put valid line to '1' . and all things .....but now I am getting a totally different output ....attached picture.

I am really confused what it is ...... 

FFT core 9.0 configuration also attached , if you find any mistake in that please let me know.

[train04]

Really Thanks D@n 

I am sorry for the writing mistake, yes it was FFT IP CORE 9.0....... and I will try these things about valid signal.....and will come back soon to you with my output.

[train04]

Sorry for the inconvenience D@n

 I am using a XIlinx DDS core for generating a 20KHz sine wave.....in the picture first wave is output of DDS core...

next I am giving this to xilinx FFT core 6.0  direct without using FIFO......which is shown as second wave down to sine wave....

It is generating frequency spectrum but that is not correct spectrum of sine wave,....... when I used a sine wave of same frequency in MATLAB it gives only one peak .... but as we seen here lots of peaks are coming .....which gives problem for me......

now can you help me ..... may be my IP core customization is not proper........

[D@n]

@train04,

It might help if you told me what I was looking at.  None of the plots are marked.

However, judging from the output alone, it looks like you are doing something with the valid signal that doesn't make sense.  It's hard to be conclusive, though, since I don't know what the traces are.

Dan

[train04]

Thanks D@n ...... now i am getting my correct sine wave........

I have given this sine wave to FFT core and I am getting output shown in picture.......but when i have checked in MATLAB it was different ...so can you please help me to find error in this output. 

CLK using ----------------------- 100MHz.

Frequency of sine wave ------ 20KHz

sampling Frequency ---------- 50KHz

 

[D@n]

@train04,

That might just be a viewer issue.  Make sure your waveform viewing tool knows that your output is supposed to be signed.

Dan

[train04]

HIII D@n,

  I now i am using DDS core for generating Sine wave for giving as input to FFT core , i am getting output but it is not actual sine wave , I know it is periodic signal but it has different shape ... I am attaching my picture of output , so you can help

I am using Xilinx DDS core of 6.0 , ..

 

[D@n]

@train04,

Just holler when/if you get stuck.  Debugging FFT's has always been a fun challenge of mine.

Dan

[jpeyron]

Hi @train04,

I do not have experience with using the FFT IP. Here is a project that uses the FFT IP core. Unfortunately it does not use microblaze. Here is the Fast Fourier Transform v9.0 LogiCORE IP Product Guide that should be helpful. 

thank you,

Jon

[D@n]

@train04,

Yeah, okay, pardon me for saying but ... just "wiring it up" is going to take you down a rabbit hole unless you know how to debug what you've then wired up.

Allow me to suggest a different approach: build a design that you can interact with both in simulation and on the actual hardware.  As part of this interaction, feed the values from your .CSV file into your design and verify that you are getting the right result.  If you add any more elements than are necessary for just that test, then you'll never know what's going wrong when things fail.

Dan

[train04]

Thanks ,

Actually I am beginner for ARTY , I have a (.CSV)  format sampled ADC signal ... I want FFT of that .so how to start and use FFT core...that help I want ...I am really struggling  with it ....Please give some solution.

[D@n]

@train04,

I'm not quite sure I understand.  An FFT is not normally a bus-based peripheral such as microblaze would be able to see and interact with.  Can you share some more details about 1) what you've done, 2) what you are expecting to happen as a result, and 3) what it is you want to have happen?

Thanks,

Dan