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xc6lx45

CMOD A7: standard FTDI JTAG access not working

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Hi,

I am trying to make conventional FT2232H JTAG work with the CMOD A7. The method is standard and has been used for many years (e.g. xc3sprog.exe), my code works with many other boards, including the Digilent-licensed adapters sold by Trenz-Elektronik.

My board itself is functional (Vivado Hardware manager recognizes it correctly), but I can't get my own JTAG code to work: The data readback pin of the JTAG interface appears to be stuck on HIGH. Any attempt to read IDCODE, or loop data through BYPASS mode, returns all-ones 0xFF.

Unfortunately, there is a missing page in the schematic: The TMS, TCK, TDI_FPGA and TDO_FPGA lines (page 2 quadrant B2) seem to go nowhere.

My question: Can you please provide the necessary information to make a "conventional" FTDI JTAG interface work with this board? It would be a very interesting module, but I need my own JTAG ...
Maybe I'm missing only some GPIO settings for the remaining pins of the FT2232H bank, but without documentation there isn't much I can do.

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Follow-up: This picture is from the reference manual section 6. Four signals => CLK, TDO, TDI, TMS. Direct connection between FTDI chip and FPGA, as is standard.
So I guess I'm not asking anything unreasonable here.

 

a.png

Edited by xc6lx45

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Thanks a bunch. It works now, even with clock divider zero (30 MHz CLK).

While we're here, could you please advise what to do with the remaining ADBUS and ACBUS GPIOs?

For example, it does not work when driving ADBUS4 high, so it seems to be connected somewhere. What should I do with those, configure all as input, or drive low maybe?

I'd like to avoid any "loose ends" like undriven / weakly driven digital inputs, two outputs on the same signal etc.

By the way, buffers for a one-inch interconnect? Maybe some muxing scheme. But if it were about signal integrity, the first thing I'd do is play with the drive levels of the FTDI chip. Right now they are at 4 mA minimum, and can be increased with FT_PROG up to 16 mA. Just thinking aloud...

 

Edited by xc6lx45
ADBUS1 => ADBUS4 corrected

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@xc6lx45,

I think you are quickly going to exhaust what Digilent is interested in sharing.  If you'd like, though, you can read the EEPROM and look at Digilent's current FT2232H configuration using libxsvf.  That might give you some information regarding what's going on within the FT2232.

Dan

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Hi D@n,

I'm not sure we're talking about the same thing here.
My question relates to the correct FTDI IO config (directions and levels) to control the board with a standard FTDI JTAG.
This is very basic usage, as known from just about any other FPGA+FTDI board seen over the last decade or so.

Right now, it is already functional (thanks again, Jon) but I'm hoping for complete instructions to drive the GPIOs "correctly and safely", avoiding stupid mistakes like no or multiple drivers on one signal. Imagine I was about to ship the design to the backwaters of China to drive 40+ tons of test equipment with thousands of JTAG transactions per second for low-latency IO. That's what my last project does on a Trenz board. So far with zero reported failures, keeping fingers crossed.

Regarding the last line in my earlier mail, I was just thinking aloud whether I could strip USD 0.00000000001 off the CMOD A7 BOM (because strictly from a four-wire JTAG hardware perspective there is no need for separate buffers). Just thinking aloud.
Anybody can download FT_PROG and fetch the EEPROM config with three mouse clicks on a Windows PC. There is nothing secret, illicit or novel about this (FT_PROG has been there since 2009).

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HI @xc6lx45,

You should tri-state the other pins (configure as inputs). The buffer isn’t necessary. We missed removing it from the design.  It has been removed from some upcoming designs.

thank you,

Jon

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