Vivado HLS

[PhDev]

Hi,

Do you have any experience of using Vivado High Level Synthesis, HLS?

Today I use VHDL and C/C++ in microblaze. I am interested in testing HLS but don't know if it is worth spending time on that.

Is it easy to get things running using HLS?

What are the main pro/cons using HLS instead of VHDL/Verilog?

Are the tools mature?

Best regards

[JColvin]

Hi @PhDev,

I have moved your question to a different section of the Forum where some of the other engineers on the Forum with knowledge (or at least thoughts) on HLS will be more likely to see it.

Personally, I haven't used Vivado HLS and from my understanding Digilent has almost no material on it aside from potentially a couple of SDSoC platforms (which I haven't looked into so I don't know this for certain).

In terms of using HLS itself (again, having not used it), I imagine it will (unsurprisingly) boil down to a blend of personal taste and design requirements. It certainly seems attractive if you are experienced in C code and not HDL but want to use FPGA/SoC resources. But if you have some pretty strict requirements in terms of how the process goes and can already do it in HDL, is it worth putting the time in to learn a new design flow?

On the mature side of the tools, Xilinx felt comfortable enough releasing them as part of the WebPACK edition of Vivado last year rather than as a separate tool, so there is that in terms of maturity; not a guarantee obviously, but something to consider at least since it would be easy enough to try out with minimal financial obligation. Xilinx does have Design Hub with a lot resources on HLS.

Thanks,
JColvin