Clock Frequency for 4 digit 7 segment display in VHDL

[eknpnr]

I am using basys 3 and VHDL to create a stopwatch and I need to do it for both the 7 segment display of the basys3 itself and for a external 4 digit 7 segment display. I am given the clock divider code for the 7 seven of the basys3 by my instructor and I managed to do the stopwatch. When I changed all my constraints to the PMOD pins and connect to the external 7 segment I can see that it works because it stops and resets but it does the counting so quickly that I can't read at all.

I am thinking that the problem may be because of the clock divider and the frequency of the clocks. The given code states that since the original clock of the basys3 is 100 MHz a counter will count up to 500000 to obtain a 100 hz and another counter will count up to 208334 that is 240 Hz.

First of all I didn't understand why the second clock is 240 Hz and why do the counters count up to these irrelivant numbers. Secondly what can I do for the external 4 bit 7 segment to slow it down?

[D@n]

@eknpnr,

Sounds like a fun project!  Indeed, this sounds like one of my own projects when I first started working on a Basys3 board.  You can still see the stopwatch, timer, clock, and alarm clock code that I built here.  (It's in Verilog)  Internally, I used a 48-bit counter to get clock precision that would take .... a long time to be noticably off.  Indeed, the 48'bit counter offers better precision that the clock driving it ...  You can read about this approach to generating an exact clock here, under techniques to generate a fractional clock.

The 7-segment display should be a separate module--uncoupled from your stop watch.  If you do the stop watch properly, you should have a seconds digit that changes on the second. Subseconds are ... bonus if you want them, or at least they were for me--I'm not sure what your instructor wants..

Dan