I am new to this forum so still getting used to things. I am trying to implement the Pmod ALS on an FPGA, and I require to comply with the SPI protocol. I understood the protocol, but the only problem I have is this.
"The PmodALS reports to the host board when the ADC081S021 is placed in normal mode by bringing the CS pin low, and delivers a single reading in 16 SCLK clock cycles. The PmodALS requires the frequency of the SCLK to be between 1 MHz and 4 MHz. The bits of information, placed on the falling edge of the SCLK and valid on the subsequent rising edge of SCLK, consist of three leading zeroes, the eight bits of information with the MSB first, and four trailing zeroes."
As far as I know, 3+8+4=15, and not 16, so where is the extra clock cycle and what is it doing?
Is the sensor providing 4 irrelevant numbers before the 8-bit of information and then 4 irrelevant numbers again?
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spartacus28
Hi,
I am new to this forum so still getting used to things. I am trying to implement the Pmod ALS on an FPGA, and I require to comply with the SPI protocol. I understood the protocol, but the only problem I have is this.
"The PmodALS reports to the host board when the ADC081S021 is placed in normal mode by bringing the CS pin low, and delivers a single reading in 16 SCLK clock cycles. The PmodALS requires the frequency of the SCLK to be between 1 MHz and 4 MHz. The bits of information, placed on the falling edge of the SCLK and valid on the subsequent rising edge of SCLK, consist of three leading zeroes, the eight bits of information with the MSB first, and four trailing zeroes."
As far as I know, 3+8+4=15, and not 16, so where is the extra clock cycle and what is it doing?
Is the sensor providing 4 irrelevant numbers before the 8-bit of information and then 4 irrelevant numbers again?
Any help will be appreciated.
Thanks.
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