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Arty-Z7-20-base-linux


Go to solution Solved by sbobrowicz,

Question

Hello,

i used the "Arty-Z7-20-base-linux"-project with Vivado 2017.2, first i copied the board files to my new installed vivado 2017.2 Installation and then i run the "create_project.tcl" script. So far so good. After that i have tried to create a hdl-wrapper, because i liked to generate a bitstream. Vivado has got the following error:

Spoiler

 

 [BD 41-1665] Unable to generate top-level wrapper HDL for the BD-design 'Arty_Z7_20.bd' is locked. Locked reason(s):
* Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
Arty_Z7_20_PWM_0_0
Arty_Z7_20_axi_dynclk_0_0
Arty_Z7_20_dvi2rgb_0_0
Arty_Z7_20_rgb2dvi_0_0

I followed the instruction and got:

report_ip_status
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
| Date         : Mon Dec 11 10:17:31 2017
| Host         : IP415 running 64-bit Service Pack 1  (build 7601)
| Command      : report_ip_status
------------------------------------------------------------------------------------

IP Status Summary

1. Project IP Status
--------------------
Your project uses 31 IP. Some of these IP may have undergone changes in this release of the software. Please review the recommended actions.

More information on the Xilinx versioning policy is available at www.xilinx.com.

Project IP Instances
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Instance Name                                | Status                  | Recommendation               | Change    | IP Name            | IP      | New Version   | New        | Original Part        |
|                                              |                         |                              | Log       |                    | Version |               | License    |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_PWM_0_0                           | IP definition not found | Add IP definition to catalog | Change    | PWM                | 2.0     | N/A           | Included   | xc7z020clg400-1      |
|                                              |                         |                              | Log not   |                    | (Rev.   |               |            |                      |
|                                              |                         |                              | available |                    | 5)      |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_axi_dynclk_0_0                    | IP definition not found | Add IP definition to catalog | Change    | axi_dynclk         | 1.0     | N/A           | Included   | xc7z020clg400-1      |
|                                              |                         |                              | Log not   |                    | (Rev.   |               |            |                      |
|                                              |                         |                              | available |                    | 3)      |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_axi_gpio_0_0                      | Up-to-date              | No changes required          |  *(1)     | AXI GPIO           | 2.0     | 2.0 (Rev. 15) | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           |                    | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 15)     |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_axi_gpio_hdmi_0                   | Up-to-date              | No changes required          |  *(2)     | AXI GPIO           | 2.0     | 2.0 (Rev. 15) | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           |                    | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 15)     |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_axi_gpio_led_0                    | Up-to-date              | No changes required          |  *(3)     | AXI GPIO           | 2.0     | 2.0 (Rev. 15) | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           |                    | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 15)     |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_axi_gpio_shield_1_0               | Up-to-date              | No changes required          |  *(4)     | AXI GPIO           | 2.0     | 2.0 (Rev. 15) | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           |                    | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 15)     |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_axi_gpio_sw_0                     | Up-to-date              | No changes required          |  *(5)     | AXI GPIO           | 2.0     | 2.0 (Rev. 15) | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           |                    | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 15)     |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_axi_mem_intercon_0                | Up-to-date              | No changes required          |  *(6)     | AXI Interconnect   | 2.1     | 2.1 (Rev. 14) | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           |                    | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 14)     |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_axi_vdma_0_1                      | Up-to-date              | No changes required          |  *(7)     | AXI Video Direct   | 6.3     | 6.3 (Rev. 1)  | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           | Memory Access      | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 1)      |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_axi_vdma_1_0                      | Up-to-date              | No changes required          |  *(8)     | AXI Video Direct   | 6.3     | 6.3 (Rev. 1)  | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           | Memory Access      | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 1)      |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_axis_subset_converter_0_0         | Up-to-date              | No changes required          |  *(9)     | AXI4-Stream Subset | 1.1     | 1.1 (Rev. 13) | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           | Converter          | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 13)     |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_axis_subset_converter_1_0         | Up-to-date              | No changes required          |  *(10)    | AXI4-Stream Subset | 1.1     | 1.1 (Rev. 13) | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           | Converter          | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 13)     |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_clk_wiz_0_0                       | Up-to-date              | No changes required          |  *(11)    | Clocking Wizard    | 5.4     | 5.4 (Rev. 1)  | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           |                    | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 1)      |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_dvi2rgb_0_0                       | IP definition not found | Add IP definition to catalog | Change    | dvi2rgb            | 1.7     | N/A           | Included   | xc7z020clg400-1      |
|                                              |                         |                              | Log not   |                    | (Rev.   |               |            |                      |
|                                              |                         |                              | available |                    | 1)      |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_proc_sys_reset_0_0                | Up-to-date              | No changes required          |  *(12)    | Processor System   | 5.0     | 5.0 (Rev. 11) | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           | Reset              | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 11)     |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_proc_sys_reset_0_1                | Up-to-date              | No changes required          |  *(13)    | Processor System   | 5.0     | 5.0 (Rev. 11) | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           | Reset              | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 11)     |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_proc_sys_reset_0_2                | Up-to-date              | No changes required          |  *(14)    | Processor System   | 5.0     | 5.0 (Rev. 11) | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           | Reset              | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 11)     |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_proc_sys_reset_0_3                | Up-to-date              | No changes required          |  *(15)    | Processor System   | 5.0     | 5.0 (Rev. 11) | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           | Reset              | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 11)     |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_processing_system7_0_0            | Up-to-date              | No changes required          |  *(16)    | ZYNQ7 Processing   | 5.5     | 5.5 (Rev. 5)  | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           | System             | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 5)      |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_processing_system7_0_axi_periph_0 | Up-to-date              | No changes required          |  *(17)    | AXI Interconnect   | 2.1     | 2.1 (Rev. 14) | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           |                    | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 14)     |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_rgb2dvi_0_0                       | IP definition not found | Add IP definition to catalog | Change    | rgb2dvi            | 1.3     | N/A           | Included   | xc7z020clg400-1      |
|                                              |                         |                              | Log not   |                    | (Rev.   |               |            |                      |
|                                              |                         |                              | available |                    | 2)      |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_rst_processing_system7_0_100M_0   | Up-to-date              | No changes required          |  *(18)    | Processor System   | 5.0     | 5.0 (Rev. 11) | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           | Reset              | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 11)     |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_rst_processing_system7_0_142M_0   | Up-to-date              | No changes required          |  *(19)    | Processor System   | 5.0     | 5.0 (Rev. 11) | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           | Reset              | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 11)     |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_v_axi4s_vid_out_0_0               | Up-to-date              | No changes required          |  *(20)    | AXI4-Stream to     | 4.0     | 4.0 (Rev. 6)  | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           | Video Out          | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 6)      |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_v_tc_0_0                          | Up-to-date              | No changes required          |  *(21)    | Video Timing       | 6.1     | 6.1 (Rev. 10) | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           | Controller         | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 10)     |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_v_tc_1_0                          | Up-to-date              | No changes required          |  *(22)    | Video Timing       | 6.1     | 6.1 (Rev. 10) | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           | Controller         | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 10)     |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_v_vid_in_axi4s_0_0                | Up-to-date              | No changes required          |  *(23)    | Video In to        | 4.0     | 4.0 (Rev. 6)  | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           | AXI4-Stream        | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 6)      |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_xadc_wiz_0_0                      | Up-to-date              | No changes required          |  *(24)    | XADC Wizard        | 3.3     | 3.3 (Rev. 3)  | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           |                    | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 3)      |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_xlconcat_0_0                      | Up-to-date              | No changes required          |  *(25)    | Concat             | 2.1     | 2.1 (Rev. 1)  | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           |                    | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 1)      |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_xlconcat_1_0                      | Up-to-date              | No changes required          |  *(26)    | Concat             | 2.1     | 2.1 (Rev. 1)  | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           |                    | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 1)      |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Arty_Z7_20_xlconstant_0_0                    | Up-to-date              | No changes required          |  *(27)    | Constant           | 1.1     | 1.1 (Rev. 3)  | Included   | xc7z020clg400-1      |
|                                              |                         |                              |           |                    | (Rev.   |               |            |                      |
|                                              |                         |                              |           |                    | 3)      |               |            |                      |
+----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+
*(1) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/axi_gpio_v2_0/doc/axi_gpio_v2_0_changelog.txt
*(2) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/axi_gpio_v2_0/doc/axi_gpio_v2_0_changelog.txt
*(3) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/axi_gpio_v2_0/doc/axi_gpio_v2_0_changelog.txt
*(4) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/axi_gpio_v2_0/doc/axi_gpio_v2_0_changelog.txt
*(5) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/axi_gpio_v2_0/doc/axi_gpio_v2_0_changelog.txt
*(6) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/axi_interconnect_v2_1/doc/axi_interconnect_v2_1_changelog.txt
*(7) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/axi_vdma_v6_3/doc/axi_vdma_v6_3_changelog.txt
*(8) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/axi_vdma_v6_3/doc/axi_vdma_v6_3_changelog.txt
*(9) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/axis_subset_converter_v1_1/doc/axis_subset_converter_v1_1_changelog.txt
*(10) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/axis_subset_converter_v1_1/doc/axis_subset_converter_v1_1_changelog.txt
*(11) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/clk_wiz_v5_4/doc/clk_wiz_v5_4_changelog.txt
*(12) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt
*(13) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt
*(14) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt
*(15) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt
*(16) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/processing_system7_v5_5/doc/processing_system7_v5_5_changelog.txt
*(17) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/axi_interconnect_v2_1/doc/axi_interconnect_v2_1_changelog.txt
*(18) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt
*(19) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt
*(20) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/v_axi4s_vid_out_v4_0/doc/v_axi4s_vid_out_v4_0_changelog.txt
*(21) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/v_tc_v6_1/doc/v_tc_v6_1_changelog.txt
*(22) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/v_tc_v6_1/doc/v_tc_v6_1_changelog.txt
*(23) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/v_vid_in_axi4s_v4_0/doc/v_vid_in_axi4s_v4_0_changelog.txt
*(24) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/xadc_wiz_v3_3/doc/xadc_wiz_v3_3_changelog.txt
*(25) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/xlconcat_v2_1/doc/xlconcat_v2_1_changelog.txt
*(26) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/xlconcat_v2_1/doc/xlconcat_v2_1_changelog.txt
*(27) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/xlconstant_v1_1/doc/xlconstant_v1_1_changelog.txt

 

As you can see, the reason is: "IP definition not found" for the listed ip-cores (see error message).

Can you tell me, what i should do?

What is a "Petalinux-Arty-Z7-20-2017.2-2.bsp" file and what is it good for?

Thank you...

Edited by JColvin
put in spoiler for visual compactness
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That project doesn't have an official release package, so you need to download it from a git shell using the following command:

git clone --recursive https://github.com/Digilent/Arty-Z7-20-base-linux.git

The reason this is necessary is because the project contains the vivado-library IP repo as a git sub-module. The github "Download ZIP" button does not correctly include sub-modules. 

The .bsp file is imported into the petalinux toolset in order to create a petalinux project that properly works with this block diagram. For more information on this, see the README for the Arty Z7-20 petalinux project: https://github.com/Digilent/Petalinux-Arty-Z7-20#generate-project . 

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