Question

Vivado 2017.2 Windows 10 - I am a Vivado newbie

I am trying to use the Arty board for some prototyping, I am trying to make my own new Block Design to instantiate in  my new project,

I grabbed the ethernet-lite reference design,  I upgraded all IP. Added my new blocks, and generated. I am getting issues with the MIG, I checked the pinout of the symbols and it seems correct to match my axi_mem controller M0. I tried to re-customize the MIG_7series IP, the pinout seems correct against the reference design board.prj. . I checked the datasheet of the reference design and entered everything the same.

I generated the block design selected Synthesis option as global : here are my errors:

  • Block Design (6 errors):
  • set_property -name {CONFIG.BOARD_MIG_PARAM} -value {ddr3_sdram} -objects [get_bd_cells mig_7series_0]
  • [filemgmt 56-285] srcscanner execution failed with return code -1073741511.
  • [filemgmt 56-285] srcscanner execution failed with return code -1073741511.
  • [filemgmt 56-285] srcscanner execution failed with return code -1073741511.
  • [filemgmt 56-285] srcscanner execution failed with return code -1073741511.

  If I ignore them and try to move forward I get errors in my other project about the MIG.

Maybe I am missing something basic - looking for suggestion/solution/approach?

Glenn

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Hi @gsandy,

Could you attach a screen shot of you block design. Did you install the board files here? Have you looked at the resource center here.  The resource center has additional mig info available in the addition resources section: Arty Xilinx MIG Resources. Could you clarify on this statement "f I ignore them and try to move forward I get errors in my other project about the MIG."?

thank you,

Jon

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I have attached the Block design. I will get the board_files and retry. I have tried numerous runs and I was able to package the BD and include it in my new top design. It would report failure to create customized MIG.

project1_bd.JPG

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