Question

Hello,

i'am still trying send "Hello World" to my terminal. I made a simple design in vivado and use the uartlite ip. But i cant generate the Bitstream because of undefined ports:

"[DRC NSTD-1] Unspecified I/O Standard: 2 out of 132 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: uart_rtl_rxd, and uart_rtl_txd."

So i tried to solve that issue, but i dont know which pins i should connect with the used ports. I thought, that i should read the manual, but the manuel gives me no answer!

The page where J14 (USB-UART-Bridge) should be decribed is lost - maybe in the deep space or in an black hole?

Where is the schematic for the Arty-Z7-20 board? I dont mean the one, where J14 is gone away.

My trust in you is nearly gone...

Thank you...

Edited by JColvin
edited for language

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Hello,

We are more than happy to answer your questions, but this is a public forum and you need to take care of your bad language. The page with the J14 (USB-UART-Bridge) is not lost. In the Arty Z7 datasheet there are pages left intentionally blank, that is because it is our decision what we want to publish. 

You work on Arty z7 board, if you open  the Zinq ip-core, in the PS zone you will find listed in the I/O Peripherals, the UART1 and UART0. You can manually select both of them. More than that, Vivado comes in your help and  after you select "Run Block Automation " and "Run Connection Automation " the UART0 will be automatically selected. Basically if you want to make a "Hello World" application, your Block Design only needs to contain the Zynq ip-core. That's all. If you still need more assistance please tell me and I will gladly respond to your questions.

Cheers,

Vanca Bogdan

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system.pdf

Hello Vanca Bogdan,

yes you are right, my language is bad and i apologise for that. But if i do what you told me, i can not reach my Goal.

I deleted my small design and placed a Zynq ip-core - only that; then i run "block Automation" and after that "Generate Bitstream". So i get three Errors:

[BD 41-758] The following clock pins are not connected to a valid clock source:
/processing_system7_0/M_AXI_GP0_ACLK

[BD 41-1031] Hdl Generation failed for the IP Integrator design C:/Projekte/Masterthesis/Vivado/PU/PU.srcs/sources_1/bd/system/system.bd

[Vivado 12-4756] Launch of runs aborted due to earlier errors while preparing sub-designs for run execution.

To solve These errors i add the System Clock from the Arty Z7-20 ip-core section as you can see in the attached System.pdf.

I earned that:

[DRC NSTD-1] Unspecified I/O Standard: 1 out of 132 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: reset_rtl.
 

and

[DRC UCIO-1] Unconstrained Logical Port: 1 out of 132 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: reset_rtl.
 

So what do i wrong? Do i have the wrong inner attitude?

I will write my Thesis and i Need a Linux based SoC because i have a fantastic idea - but it seems - i have no luck...

Thank you...

 

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