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[deppenkaiser]

Hello,

the online Manual wrotes: "[...] The Zynq presets file (available in the Arty Z7 Resource Center) takes care of mapping the correct MIO pins to the UART 0 controller and uses the following default protocol parameters: 115200 baud rate, 1 stop bit, no parity, 8-bit character length. [..]"

Where are the files?

What Name do they have?

How do i use them?

Thank you...

[artvvb]

@deppenkaiser

The UART is instantiated and the UART pins are mapped as part of the "Run Block Automation" process, which applies the Zynq preset contained in the board file. You can configure the UART by customizing the Zynq IP. The UART is represented in the block design as a part of the FIXED_IO interface of the Zynq block. In addition, the UART connection cannot be used in a pure-HDL project.

Thanks,

Arthur

[BogdanVanca]

Hello,

This guide will help you obtain Vivado Board Files for the Nexys 4, Nexys 4 DDR, Basys 3, Arty, Nexys Video, Zedboard and Zybo FPGA Boards.

https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1

Also I attach to you the link to the  repository that contains the board files used by Vivado.

https://github.com/Digilent/vivado-boards

cheers,

Vanca Bogdan

[deppenkaiser]

Hello Bogdan Vanca,

i have allready installed these files. If i create a new project, then i can choose the Arty-Z7-20 board as plattform.

My Problem ist: I like to use the UART and in the board's ip-tab are some ip's for my board, but no ip for the UART. If  i take the ip "uartlite" from Xilinx then i have not the right configuration and the Operation "Generate Bitstream" fails. So once again: "[..] takes care of mapping the correct MIO pins to the UART 0 controller and uses the following default protocol parameters: 115200 baud rate, 1 stop bit, no parity, 8-bit character length [..]". How do i connect or use or configure a design, that i can use the UART?

Thank you.

[deppenkaiser]

@artvvb

Thank you, now it works.

I have an other question. I used the "Hello World" example in the SDK and it was good; how can i write code for both cores of the A9 (bare metal)?

Thank you...

[jpeyron]

Hi @deppenkaiser,

Here is a video that shows using multiple cores with the zybo. I believe it would be the same think for the Arty-Z7. Here is a forum thread that discusses using multiple elfs in different cores.  

cheers,

Jon