• 0
hassan_3md

Filter using FIR compiler RFD is delayed

Question

I have build filter using FIR compiler. It is filtering the input quite well. I used COE generated from Matlab. I have two problems.

1- filter latency is 39 cycles. I am getting my RDY signal high after around 39 cycles. But RFD gets high after 251 cycles? I don't understand , if filter is giving me RDY signal high then according to FIR compiler datasheet figure of MAC multiplier timings, i should get  RFD as soon as RDY gets high. I have tried both systolic and transpose MAC. I am attaching the figures from chip-scope.

ZOOM-IN of ND-RFD

rfd_nd.thumb.jpg.a8b8731a5ddd7adb1259f34115139be1.jpg

ZOOM-IN of RDY

rfd_nd_rdy.thumb.jpg.b5aa83fdf605502fd449fd6e4f28c26b.jpg

ZOOM-OUT including two RFDs

rfd_nd_rdy_next.thumb.jpg.0f504c0fda64d0d6c11d0cd50d193387.jpg

I want to get RFD as soon as my filter output is ready. Any clue !

 

2.All is fine. filtering is good. I am using filter range from 900hz-3300hz. I am getting TICK like sound after some 500msec. I saw it on oscilloscope it is some type of clipped signal containing 5-6 cycles of not any specific frequency. the signal is looking more like square wave due to clipping. I am getting that TICK sound even if I did not attach LINE IN cable (from which data is fed to filter input through CODEC). But if I programmed the input of filter to '0' in verilog, I get nothing. Tick sound is also removed now :P . Filter is generating tick sound in any other condition, What is this? am I getting overflow some where? 

Thanks

 

Share this post


Link to post
Share on other sites

10 answers to this question

Recommended Posts

  • 0

@hassan_3md,

I just read through what you wrote above, and ... I'm struggling to understand what you are doing.  It sounds like one signal is a filter input signal and one is a filter output signal, but you are presenting three signals above.  Can you please define your three signals and tell us how they relate to your filter and signal processing chain?

Dan

Share this post


Link to post
Share on other sites
  • 0
19 hours ago, D@n said:

@hassan_3md,

I just read through what you wrote above, and ... I'm struggling to understand what you are doing.  It sounds like one signal is a filter input signal and one is a filter output signal, but you are presenting three signals above.  Can you please define your three signals and tell us how they relate to your filter and signal processing chain?

Dan

These are control signals. I didn't show data signals. RDY is output signal when Filter output is available on bus . RFD ( Read For Data) is output signal, tells When filter is ready for input . ND is input valid signal for New Data.

according to FIR compiler data sheet RFD should get high as soon as RDY gets high.

Share this post


Link to post
Share on other sites
  • 0

@hassan_3md,

A couple questions ...

  1. Which version of the FIR compiler are you using?  I'm checking the v5.0 manual, is this the version you are using?
  2. Can you share with us how you configured your filter?
  3. Specifically, I'm wondering how you defined the "Sample Period" of the filter.

Thanks,

Dan

Share this post


Link to post
Share on other sites
  • 0
On 12/7/2017 at 4:45 PM, D@n said:

@hassan_3md,

A couple questions ...

  1. Which version of the FIR compiler are you using?  I'm checking the v5.0 manual, is this the version you are using?
  2. Can you share with us how you configured your filter?
  3. Specifically, I'm wondering how you defined the "Sample Period" of the filter.

Thanks,

Dan

Thanks Dan. I got the first part of my question.  version is 5.0. I used 16000Hz for filter . So I will get next RFD after 62.5 usec. But If i will delay the ND insertion after getting RFD high. I will get RFD after 62.5us after ND insertion. So to avoid latency to match 1600hz sampled input, i have to insert ND exactly at the same time as RFD get high.

 

I still did not get my second part right.

"2.All is fine. filtering is good. I am using filter range from 900hz-3300hz. I am getting TICK like sound after some 500msec. I saw it on oscilloscope it is some type of clipped signal containing 5-6 cycles of not any specific frequency. the signal is looking more like square wave due to clipping. I am getting that TICK sound even if I did not attach LINE IN cable (from which data is fed to filter input through CODEC). But if I programmed the input of filter to '0' in verilog, I get nothing. Tick sound is also removed now :P . Filter is generating tick sound in any other condition, What is this? am I getting overflow some where? "

I have tried different windows with different order of filters.I am generation COE file from MATLAB. any clue Why i am getting TICK sound in my filter output?

Share this post


Link to post
Share on other sites
  • 0

@hassan_3md,

I'm not sure why you are getting a ticking sound ... there are just too many possibilities to be dogmatic about it, sorry.

What I will say is ... I've gotten ticking sounds in the past in a couple of places, and perhaps that might suggest some places to look.  So, in my experience, here are some places I've gotten annoying ticking sounds:

  1. When my code starts or stops.  You'll recognize this easily enough because it only happens once at the beginning (or end) of a test.
  2. Between buffers, if you don't keep the data filled.  For example, if you miss a ND opportunity, or if there is any other discontinuity in your source data, you might get annoying clicks.
  3. You may also hit this problem if you are using two separate clocks--one to generate the data and the D/A clock that is reading the data.

Be aware that the clicks may not show up during simulation, so you may wish to be prepared to chase them down while the design is running.  I'd start by using an LED and checking, internally, whether or not you are meeting your own timing requirements.  If you can succeed there, your next step will be to use that as a trigger for some type of internal scope.  (Vivado calls theirs an ILA, open source options exist through)

Dan

Share this post


Link to post
Share on other sites
  • 0
On 12/14/2017 at 4:38 PM, D@n said:

@hassan_3md,

I'm not sure why you are getting a ticking sound ... there are just too many possibilities to be dogmatic about it, sorry.

What I will say is ... I've gotten ticking sounds in the past in a couple of places, and perhaps that might suggest some places to look.  So, in my experience, here are some places I've gotten annoying ticking sounds:

  1. When my code starts or stops.  You'll recognize this easily enough because it only happens once at the beginning (or end) of a test.
  2. Between buffers, if you don't keep the data filled.  For example, if you miss a ND opportunity, or if there is any other discontinuity in your source data, you might get annoying clicks.
  3. You may also hit this problem if you are using two separate clocks--one to generate the data and the D/A clock that is reading the data.

Be aware that the clicks may not show up during simulation, so you may wish to be prepared to chase them down while the design is running.  I'd start by using an LED and checking, internally, whether or not you are meeting your own timing requirements.  If you can succeed there, your next step will be to use that as a trigger for some type of internal scope.  (Vivado calls theirs an ILA, open source options exist through)

Dan

Thanks Dan a lot for a fruitful insight. 

1.It always happened in periodic manner. Some time upon changing filter order I get the difference that If my audio input is idle (means there may some noise floor but no signal ), at order of 40 there is not Tick sound but When I give some input signal to be filtered I start to get Tick sound. And if I increase or decrease order I get Tick sound even in Idle (only with noise floor)

2.I am sure that I am not missing any data.First I was thinking that I might missing, but now I am sure that I am not. Because I have FIFO of 16 depth. From ADC data enters in FIFO at the speed of 16000 Hz. As soon as FIFO gets non-empty I read the data back and insert ND. And FIFO remain empty for around 62.5 us (as data is coming in at 16000hz) . So my FIFO fullness always 1 then 0, 1 then 0 and so on although FIFO can store upto 16. So am I right that I am not missing any data? please correct me if there can be other possibility?

3. clock is same for ADC and DAC. I am using on board codec on ML403. yes Filter clock is 100 MHz. If I bypass filter and direct the output of FIFO to DAC it works fine.

I will look all these options again and confirm these. It may be due to Quantization of coefficients? or some thing like this?

 

Thanks

Hassan

Share this post


Link to post
Share on other sites
  • 0

@hassan_3md,

If you've desk checked your code and desk checked your code and can't find the bug, then it's time to either

  • dig into your simulation/test bench capability to give it the fidelity necessary to reproduce your bug, or
  • use some form of internal scope to see what's going on.

I've tended to build my own scope, although Xilinx has their options.  If you do choose to use a scope of some type, you might find it valuable to limit the samples the scope collects to only those samples where the data is changing--hence try to see if you can get one scope sample per D/A sample.

Dan

Share this post


Link to post
Share on other sites
  • 0
11 hours ago, D@n said:

@hassan_3md,

If you've desk checked your code and desk checked your code and can't find the bug, then it's time to either

  • dig into your simulation/test bench capability to give it the fidelity necessary to reproduce your bug, or
  • use some form of internal scope to see what's going on.

I've tended to build my own scope, although Xilinx has their options.  If you do choose to use a scope of some type, you might find it valuable to limit the samples the scope collects to only those samples where the data is changing--hence try to see if you can get one scope sample per D/A sample.

Dan

Thanks dan

I will look into these options too. Simulation looks good probing tip.

Share this post


Link to post
Share on other sites
  • 0

Hello i am getting the same problen of clipping output in fir compiler 5.0 core...plz let me know if it has been resolved? Everything is ok..simple sin wave filteration gives the correct result but when i try to input the real and imaginary signal it doesnot give the peak....so plz do let me know. I am struggling this from many weeks..

Share this post


Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now