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chuchang

Interfaceing FPGA and an external chip and timing constraints

Question

Hi t all, actually I new to programming, some places may be completely unknown, but a period of time, I need to do some procedures to detect, but appear in the process of the problem is not so easily solved for me, so I want to seek some help. I have designed a system using Artix-7 FPGA on a custom board. The goal is to transfer 32 bit data to an external on-board chip whose data bus is an inout port. First, a little background:

The external chip is driven by a 100MHz clock which is generated by the FPGA, let's call it o_clk. The FPGA generates this clock through an MMCM in the Memory Interface Generator (MIG IP) using the 200MHz differential system clock. The o_clk is looped back from the FPGA's output and is given to another ball as an input clock, let's call it i_clk.

The external chip receives the o_clk and sees data on this clock's rising edge. However, when the external chip sends data back to FPGA, the FPGA sees this data on the looped back i_clk. The idea behind doing so is that we can treat communications as source synchronous, in both the directions (remember, it is an inout port). Something like below:

FPGA --> EC is synchronous to FPGA because FPGA generates clock
EC   --> FPGA is synchronous to EC because FPGA gets external clock (virtually from EC)

To constrain this design, I have used the i_clk to set input delays on the io_data and have used the o_clk to constrain output on the same io_data bus. I have made sure I am using a forwarded clock (create_generated_clock)(using the ODDR2) for the set_output_delay constraint.

Here are my constraints:

create_clock -period 10.000 -name i_clk -waveform {0.000 5.000} [get_ports i_clk]
set_clock_groups -name loopback_grp -asynchronous -group [get_clocks i_clk] -group [get_clocks o_clk]

set_input_delay -clock i_fx3_pclk -max 8.000 [get_ports io_fx3_fdata]
set_input_delay -clock i_clk -min 2.000 [get_ports io_data]

set_output_delay -clock o_clk -max 2.000 [get_ports io_data]
set_output_delay -clock o_clk -min -0.500 [get_ports io_data]

The system seems to work properly when I run it on hardware, but I still have some doubts because I am still an amateur FPGA developer and this is my first big FPGA design.

My questions are:

  1. Have I designed a good system?
  2. Is it correct to treat the communication from EC http://www.kynix.com/Detail/390575/EC.html  --> FPGA as source synchronous? (The other direction is source sync because FPGA is providing clock, if I am not wrong.!)
  3. Are my constrains correct?

Many thanks!

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Hi @chuchang,

Welcome to the forums! Sounds like an interesting project. Digilent typically does not evaluate non-Digilent product designs. Maybe one of the more experience community members will have some input for you.

thank you,

Jon

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@chuchang,

  1. Have you designed a good system?  There's much more to good system design than you have presented.  Indeed there's more to a good system design than you could present on this channel.
  2. Can you assume a source synchronous circuit?  I couldn't find the data sheet to tell.  Your link pointed me to one of many products, not the single product with data sheet that you were using.
  3. As for whether or not you have the right constraints, I have yet to apply constraints to inputs, so I don't know.

Sorry I couldn't be of any more help,

Dan

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On 2017/12/6 at 4:08 AM, jpeyron said:

Hi @chuchang,

Welcome to the forums! Sounds like an interesting project. Digilent typically does not evaluate non-Digilent product designs. Maybe one of the more experience community members will have some input for you.

thank you,

Jon

Thnak you John, so glad to join here!

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On 2017/12/6 at 7:13 AM, D@n said:

@chuchang,

  1. Have you designed a good system?  There's much more to good system design than you have presented.  Indeed there's more to a good system design than you could present on this channel.
  2. Can you assume a source synchronous circuit?  I couldn't find the data sheet to tell.  Your link pointed me to one of many products, not the single product with data sheet that you were using.
  3. As for whether or not you have the right constraints, I have yet to apply constraints to inputs, so I don't know.

Sorry I couldn't be of any more help,

Dan

It doesn't matter, you reply makes me feel comfortable, a good day!

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Hi @chuchang

In my humble opinion contraints on your 100 MHz clock are too relaxed.  I would keep delay within 0.2 ns.

Also, I would put constraints on the output data lines delay, especially if you are sending parallel data. The same should be done on the data coming from your external source.

Hope you find this useful, good luck!

 

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