XADC sampling and acquisition timing

[drewphysics]

I have a BASYS3 board and am using the XADC to measure input voltages on pins 1 and 7 of JXADC.  I am using the XADC in continuous single channel mode by wiring .eoc_out into .den_in, and putting a DC voltage (0-1 volt) into pin 1 (and tying pin 7 to ground).  Then I display the XADC output on the 4-digit display and it looks right.  But I have a question about the timing, as I now want to put voltage signals in that have an AC component.

I'm looking at the document ug480_7Series_XADC.pdf for the timing, and see a diagram on page 72 that I believe applies.   I've attached it.

The diagram shows 2 EOC pulses, and the timing for conversion N and acquisition for N+1 that happens at the same time.   Do I assume that the 2nd EOC pulse in this diagram belongs to conversion N, so that if I use .eoc_out to latch the data, I will get the data for conversion N?

[JColvin]

Hello @drewphysics,

I believe that should be accurate, at least based on the Conversion Phase paragraphs split between pages 72 and 73 since they say EOC will be pulsed high for one DCLK cycle when the conversion results have been transferred to the output registers and apply to the last enabled channel (in this case, channel N).

Let us know if you have any more questions.

Thank you,
JColvin

[drewphysics]

1 hour ago, JColvin said:

Hello @drewphysics,

I believe that should be accurate, at least based on the Conversion Phase paragraphs split between pages 72 and 73 since they say EOC will be pulsed high for one DCLK cycle when the conversion results have been transferred to the output registers and apply to the last enabled channel (in this case, channel N).

Let us know if you have any more questions.

Thank you,
JColvin

Thanks!   So here's a followup: if it's converting and acquiring at the same time, it must be using both of the ADCs, so does that mean it's switching between the two ADCs all the time without my having to do anything?   

[JColvin]

@drewphysics,

It'll depend on what mode you are in (most of Chapter 4 in the user guide), but it looks like it powers up in a default mode where most things are automatically handled, although I'm not certain if both channels are sampled simultaneously or alternately.

Thanks,
JColvin

[drewphysics]

9 hours ago, JColvin said:

@drewphysics,

It'll depend on what mode you are in (most of Chapter 4 in the user guide), but it looks like it powers up in a default mode where most things are automatically handled, although I'm not certain if both channels are sampled simultaneously or alternately.

Thanks,
JColvin

Ok thanks, I'll take a look at that again and will do some tests.   I am pretty sure that my minimal instantiation does use both ADCs as I see the eoc_out signal every 1us.

Another question, if you don't mind: what about the dedicated V_N and V_P inputs - are they wired up?   From what I can tell on the BASYS3, we have 4 pairs of VAUX, and that's about it?   I looked at the ARTIX7 pin sheet and see that there is a pair VN_0 and VP_0 on pins B13 and A12, and these are grounded on the BASYS3 board.   Are those the dedicated analog inputs?   Just checking to be sure I'm understanding.   Thanks again for all of your help.

[artvvb]

@drewphysics

The V_N and V_P pins are indeed grounded on the Basys 3. You can find all of the connected pairs of XADC pins in the Basys 3 schematic, in Bank 35, on sheet #6.

Thanks,

Arthur

[drewphysics]

3 hours ago, artvvb said:

@drewphysics

The V_N and V_P pins are indeed grounded on the Basys 3. You can find all of the connected pairs of XADC pins in the Basys 3 schematic, in Bank 35, on sheet #6.

Thanks,

Arthur

Thanks.

I did some tests just to make sure I understand single channel continuous mode.   Here's my Verilog:

wire den_in = sw[0] ? test_out : adc_ready;
xadc_wiz_0 XADC_INST (
      .daddr_in(daddr_in),
      .dclk_in(clk20),
      .den_in(den_in),
      .di_in(data_in),
      .dwe_in(1'b0),
      .vauxp6(adc_p),
      .vauxn6(adc_n),
      .busy_out(isbusy),
      .channel_out(channel_out),
      .do_out(adc_data),
      .drdy_out(adc_data_ready),
      .eoc_out(adc_ready),
      .eos_out(eos_out),
      .alarm_out(alarm),
      .vp_in(1'b0),
      .vn_in(1'b0)
      );

As you can see, I'm using switch 0 on the BASYS3, and if it's set to 0, then I am wiring .eoc_out into .den_in.  If I set the switch to 1, then I put test_out into .den_in, and test_out is wired to one of the BASYS3 push buttons (and I'm using a 1-shot so the pulse is only 1 clock cycle wide).   Then I bring the lines "adc_ready" (from .eoc_out) and "isbusy" (from .busy_out) and "test_out" onto some pins on JB and look at it with a logic analyzer.  

The first attachment is what I see when switch 0 is off (set to 0): .busy_out and .eoc_out are free running, but there are no transitions on any of the data bits (not shown).

When I set sw[0]=1 and push the pushbutton so that I get a single pulse, I see transitions on the data lines like in the 2nd attachment.  And after looking at a few of these triggers, I can conclude that during the 1us time period where the XADC is doing it's thing, if .den_in line ("test_out") is asserted then we will get new data on the next .eoc_out after .den_in transitions.   The 2nd attachment shows this.

So, it looks like in continuous single channel mode, the XADC is sampling and converting all the time, and the only thing that .den_in does is to allow the data to be latched and presented on the .do_out lines.   

Do you know enough about the XADC to verify this?   (By the way I used the IP wizard to set instantiate it, and turned off all of the alarms and so on.   The 3 configuration registers 0, 1, 2 are 'h0016, 'h31AF, and 'h0200 respectively.)

Thanks again for your help!

   Drew

  

 

[artvvb]

I have only used Continuous Channel Sequencer mode personally (caveat for the following).

I believe that the DRP interface is largely independent of the conversion process (hence tying the den_in and eoc_out ports together). This means that data should be captured from do_out when drdy_out goes low and you have provided a stable daddr_in signal, largely ignoring the End Of Conversion signal for this process.

I am curious how you are driving daddr_in, is it tied to GPIO/Buttons/Switches, or is it floating currently? This port is the address port for the DRP interface and needs to be set. In the case of using only the AN6 channel, I believe the register address to get to the data is 6'h16.

Thanks,

Arthur

[artvvb]

I reread your post, and to answer the specific question, this sounds correct to me, but you will need to ask Xilinx to make sure, as they are the ones that created the IP.

Thanks,

Arthur

[drewphysics]

8 minutes ago, artvvb said:

I have only used Continuous Channel Sequencer mode personally (caveat for the following).

I believe that the DRP interface is largely independent of the conversion process (hence tying the den_in and eoc_out ports together). This means that data should be captured from do_out when drdy_out goes low and you have provided a stable daddr_in signal, largely ignoring the End Of Conversion signal for this process.

I am curious how you are driving daddr_in, is it tied to GPIO/Buttons/Switches, or is it floating currently? This port is the address port for the DRP interface and needs to be set. In the case of using only the AN6 channel, I believe the register address to get to the data is 6'h16.

Thanks,

Arthur

Ah, I am sorry I forgot to say that but yes, I'm setting .daddr_in to 7'h16 (isn't it a 7-bit bus?).   

I rebuilt it and brought out .drdy_out to the logic analyzer.   The attachment shows the trace.   I'm seeing this trace consistently, with the time for test_out varying (because it comes from the push button), but with .drdy_out being asserted 80ns after test_out (which is the same as .den_in).   It happens on every capture, very consistently.  

What do you think?

Thanks again!

  Drew 

 

[artvvb]

Oops, you are correct, address is seven bits.

Are your d# signals in the logic analyzer screenshots the do_out pins?

My understanding of how the XADC works is that it will continuously capture data without you doing anything. Whenever a conversion is completed, the data from that conversion is loaded into the appropriate channel's register. The eoc_out flag alerts you that there is a new piece of data to check on. Your interface for actually getting at the registers of the XADC is the DRP interface, (daddr_in, den_in, di_in, do_out, drdy_out, and dwe_in). Of these signals, we don't care about the write enable or the data input, and they should be held low. To read a value from a register, we assert den_in and daddr_in (probably at the same time), and when drdy_out is asserted, we latch the data into a reg out of do_out.

As for how to tell which sample is which, and which sample is being read, this is what the CHANNEL[4:0] signal in the timing diagram you added to the first post is for. According to page 73 of the 7Series XADC user guide, EOC, CHANNEL, and DRDY are intended to be used together, and should all represent information about the same sample. By this I mean that the second EOC should pertain to sample N.

Thanks,

Arthur

[drewphysics]

9 hours ago, artvvb said:

Oops, you are correct, address is seven bits.

Are your d# signals in the logic analyzer screenshots the do_out pins?

My understanding of how the XADC works is that it will continuously capture data without you doing anything. Whenever a conversion is completed, the data from that conversion is loaded into the appropriate channel's register. The eoc_out flag alerts you that there is a new piece of data to check on. Your interface for actually getting at the registers of the XADC is the DRP interface, (daddr_in, den_in, di_in, do_out, drdy_out, and dwe_in). Of these signals, we don't care about the write enable or the data input, and they should be held low. To read a value from a register, we assert den_in and daddr_in (probably at the same time), and when drdy_out is asserted, we latch the data into a reg out of do_out.

As for how to tell which sample is which, and which sample is being read, this is what the CHANNEL[4:0] signal in the timing diagram you added to the first post is for. According to page 73 of the 7Series XADC user guide, EOC, CHANNEL, and DRDY are intended to be used together, and should all represent information about the same sample. By this I mean that the second EOC should pertain to sample N.

Thanks,

Arthur

Many thanks.  I think I am now understanding!

One last question about the timing of the input signal.   I'm imagining a signal from a phototube maybe, it might have a 20ns rise time and then fall back to zero in a few hundred ns.  It will squirt some current onto the charging capacitor, which I believe is 3pf with a 10kOhm input impedance, so it has a charging RC time of 30ns.  Plenty fast enough if it allows the signal a full 1us before digitizing.  So,  if you run the XADC in continuous mode, and it has 2 ADCs, then is it correct that as long as your voltage signal that you want to digitize comes entirely within the period between the 2 .eoc_out signals, the capacitor will be fully charged and in the next period, the ADC will convert analog to digital?

[artvvb]

@drewphysics

Unfortunately, my personal experience with using the XADC only really applies to DC and low-frequency AC waves. You may need to take into account the additional resistors and capacitors between bank 35 and the JXADC / JA Pmod headers, as seen in the Basys 3 schematic. For the sake of other people who may be reading this, I assume that you are getting the 3pF / 10kOhm numbers from pages 29 and 30 of ug480?

To the question itself:

Quote

So,  if you run the XADC in continuous mode, and it has 2 ADCs, then is it correct that as long as your voltage signal that you want to digitize comes entirely within the period between the 2 .eoc_out signals, the capacitor will be fully charged and in the next period, the ADC will convert analog to digital?

I am not sure, I'd recommend asking Xilinx on their forums, or perhaps someone else can chime in here.

Thanks,

Arthur

[drewphysics]

On 12/6/2017 at 1:00 PM, artvvb said:

@drewphysics

Unfortunately, my personal experience with using the XADC only really applies to DC and low-frequency AC waves. You may need to take into account the additional resistors and capacitors between bank 35 and the JXADC / JA Pmod headers, as seen in the Basys 3 schematic. For the sake of other people who may be reading this, I assume that you are getting the 3pF / 10kOhm numbers from pages 29 and 30 of ug480?

To the question itself:

I am not sure, I'd recommend asking Xilinx on their forums, or perhaps someone else can chime in here.

Thanks,

Arthur

Hi Arthur.   On rereading, I realize my question was not well formed.   What I really want to know is at what time in the period between .eoc_out or .drdy_out does the XADC open the switches, disconnecting the 3pF capacitor from the input, and perform the conversion.   I am not asking about integrating the signal from the PMT, for that one has to use an op amp with a capacitor as feedback, or something similar.   Anyway many thanks for your help.

[jpeyron]

Hi @drewphysics,

I do not believe we would be able to provide you with the time in the period between .eoc_out or .drdy_out does the XADC open the switches, disconnecting the 3pF capacitor from the input, and perform the conversion. We would suggest that you reach out to Xilinx support here. 

cheers,

Jon

[salonishirodkar]

Well, you won't be able to do that with the dashboard, but I can assure you, that the XADC is more than capable to sample a 60Hz grid voltage. You will still need a suitable divider for the input though.